gnu-make

问题 Here is my makefile, i have object files in obj/ directory, and i need to compile them into binaries in bin/ folder, but somehow it doesn't work as i wanted it to work, any ideas? SOURCES= $(wildcard *.c) OBJECTS:= $(patsubst %.c, %.o, $(SOURCES)) OBJECTS:= $(addprefix obj/,$(OBJECTS)) NAMES:= $(patsubst %.c, %, $(SOURCES)) NAMES:= $(addprefix bin/,$(NAMES)) CC=gcc CFLAGS= -Wall -c -o DIRS = bin obj all: $(DIRS) $(NAMES) $(NAMES): $(OBJECTS) $(CC) -o $@ $< obj/%.o: %.c $(CC) $(CFLAGS) $@ $< $

问题 I tried to suppress an error from rm command by writing Makefile: ... clean: $(wildcard *.mod) -rm $^ 2>/dev/null ... I ran: $ make clean rm 2>/dev/null make: [clean] Error 64 (ignored) I still had gotten an error. Anyway, when I tried $ rm [some non-existent files] 2>/dev/null on the bash shell, it just works fine. How can I use 2>/dev/null inside a makefile? 回答1: The message make: [clean] Error 64 (ignored) is being printed by make after it sees that your shell command has failed. It will

问题 I have a setup where the files I want to process with make are dependent on the output of another program. Building the program and all its prerequisites is also a complicated task so I would like to use make for this as well. Now my problem is, that it doesn't seem that one can generate rules and prerequisites in Makefile recipes. Consider the following code: bar: echo target1 target2 target3 > bar foo: bar $(eval BAR := $(shell cat bar)) define FUN $(1): touch a$(1) endef ifdef BAR $

问题 For Eg., if I were to compile bunch of files in a hardware description language, I can write a Makefile in the following way analyze: a.v b.v c.v top.v vcs $(OPTIONS) a.v vcs $(OPTIONS) b.v vcs $(OPTIONS) c.v vcs $(OPTIONS) top.v Make analyze, will compile all the files in its dependency & builds the final executable. How can I write a "SINGLE Makefile rule", which will compile all its dependencies and build an executable - Mimicking the above with a rule SOMETHING LIKE: analyze: %.v vcs $

问题 How can I detect shell that will be used by gnu make? I want my make to be running on following platforms: linux windows windows with cygwin (Note that on windows with cygwin the make uses cygwin shell) Then I would like to detect if gcc is present on the system independently on OS. 回答1: So far I come up with this solution: # detect what shell is used ifeq ($(findstring cmd.exe,$(SHELL)),cmd.exe) $(info "shell Windows cmd.exe") DEVNUL := NUL WHICH := where else $(info "shell Bash") DEVNUL :=

问题 I have a master makefile which has the default values for variables and then a child makefile which includes project specific settings. At the end of the child makefile, I include the master makefile. I have been using the following code in the master makefile to set default values for a variable ifndef CC CC = avr-gcc endif And then recently I read that I can also do CC ?= avr-gcc So my question is, whether both are same and if yes which one is the recommended way of overriding variables.

问题 I have a Makefile with targets that have associated dependencies. So I use lookup table like: APPS = a b c dependency.lookup.a := x dependency.lookup.b := y dependency.lookup.c := z $(APPS): %: path/$(dependency.lookup.%).datafile do something with $(dependency.lookup.$@) This makefile gives me error. *** No rule to make target 'path/.datafile' Constraints: Only MinGW. can't use shell/MSYS. Also support FreeBSD. 回答1: This requires using Secondary Expansion feature: .SECONDEXPANSION: $(APPS):

问题 I have the following PHONY target in Makefile install: echo /usr/bin/shelldecrypt must be writable cp shelldecrypt /usr/bin When I run the target it displays the command it is executing prompt> make install OUTPUT IS echo /usr/bin/shelldecrypt must be writable /usr/bin/shelldecrypt must be writable cp shelldecrypt /usr/bin OUTPUT AS I WOULD LIKE IT /usr/bin/shelldecrypt must be writable cp shelldecrypt /usr/bin 回答1: you could add "@" before your command to surpress that echo install: @echo

问题 First the Makefile here had CFLAGS = -g -Wall -lm I was playing with C that time. Now I'm on C++ and I have to add -I eigen , quick google on it and found CXXFLAGS exist for the C++ world, while CFLAGS exist for the C world. So I updated Makefile to CFLAGS = -g -Wall -lm CXXFLAGS = -I eigen Then I found https://wiki.gentoo.org/wiki/GCC_optimization, and was inspired to updated it again CFLAGS = -g -Wall -lm CXXFLAGS = ${CFLAGS} -I eigen The complete thing: CC = g++ CFLAGS = -g -Wall -lm

问题 I'm configuring a VSCode task in tasks.json, and I need to pass the ${workspaceFolder} to a 'make' command, however it needs to be forward slashes, not back slashes. { "version": "2.0.0", "echoCommand": true, "tasks": [ { "label": "build", "type": "shell", "group": { "kind": "build", "isDefault": true }, "command": "make", "args": [ "APPDIR=\"${workspaceFolder}\"" ] . . . Is there any way to modify ${workspaceFolder} to emit forward slashes on Windows? Or, is there such a thing as a macro,