gnu-make

问题 I am reading a makefile for a Qt-created project that has the following: {backend}.cpp{release\}.obj:: $(CXX) -c $(CXXFLAGS) $(INCPATH) -Forelease\ @<< $< << (above code is using \t for recipe and is as written in makefile) Both the rule and the recipe confuse me. I'll start with {backend} in the rule. Obviously the same confusion for {release} as well. I assume this is a reference to a particular sub-directory named backend . I guess that ..\backend\release\bar.obj would be found as a

问题 From the docs: All variables that appear within the VARIABLE-ASSIGNMENT are evaluated within the context of the target: thus, any previously-defined target-specific variable values will be in effect. Note that this variable is actually distinct from any "global" value: the two variables do not have to have the same flavor (recursive vs. simple). So, given a makefile: % : foo += 1 all : x; x :: @echo '$(foo)' foo := 2 And running, I get: 2 1 1 Taking a closer look at the quote above: All

问题 I am following the solution in GNU Makefile treating each recipe line as sub-shell command without continuation character target_compile: PROJECT_SIM_OPTS += -LDFLAGS -L${CURRENT_DIR},-lm -load target_compile: copy_shared_object actual_compile_with_sim_opts @echo PROJECT_SIM_OPTS=${PROJECT_SIM_OPTS} ... When I make the Makefile, I am able to see the second target_compile fire off but not the first target_compile which has no dependencies and recipe except a variable. I tried adding override

问题 I'm trying to recompile an application already having a windows port (so it's supposed to work) Of course, you still need to run ./configure so you need MSYS or MSYS2. The configure part worked well. Now when I run make -n (so it shows which rules are executed) I get: $ make -n if test ! -f config.h; then \ rm -f stamp-h1; \ make stamp-h1; \ else :; fi ! was unexpected make: *** [config.h] Error 255 ! was unexpected is the approximate translation of a french message (so it may be slightly

问题 I want to get a better idea of my build job metrics but unfortunately, make doesn't output timestamps per se. If I run make --print-data-base , for a given target it outputs a line # Last modified 2016-08-15 13:53:16 but that doesn't give me the duration. QUESTION Is there a way to get duration of building a target without modifying each target? Some targets are inside makefiles which are generated DURING the build so not feasible to modify their recipes. POSSIBLE SOLUTION I could implement a

问题 I have a makefile setup where it accepts a command-line argument that gets parsed at build time to determine which compiler to use, CPULIST . So, I plan to build via the following command: make all CPULIST="arm x86" . I then created some phony rules so that make all loops and effectively does: make all CPULIST=x86 make all CPULIST=arm The rules: .PHONY: all all: @echo "Detected CPULIST:${CPULIST_DETECTED}" @echo "CPULIST:${CPULIST}" @for cpu in $(CPULIST_DETECTED); do \ echo "CPU:$${cpu}"; \

问题 Im running the following makefile which needs to change dir to specific target and run there npm install The problem is that I was able to see in the output that it print the directory (project/app) to the right directory but the installation (npm install) run on level up (project), why ? For example When I run it I see from cd $(DIR)/app /Users/i03432/go/src/project/app Now the second command is npm install And I got error that id doesn’t find the package json in the project path which is

问题 I'm using make --jobs=<num> to do parallel builds on a multi-core machine. I want to have a robust method to record how long it takes for a given target to get built using the pre-action, build, post-action model. This answer says: Also, start and end times are not all there is to know about how long an action takes, when you are running things in parallel; rule A might take longer that rule B, simply because rule B is running alone while rule A is sharing the processor with rules C through J

问题 In a makefile that is generated by eclipse, I see the following rules: ./Cores/$(TARGET).core.3.srec : ../$(TARGET).core.3/Debug/$(TARGET).core.3.elf @mkdir -p ./Cores/ @e-objcopy --srec-forceS3 --output-target srec "$<" "$@".temp @echo Creating srec file for CoreID\<0x826\> @head --lines=1 "$@".temp | sed 's/0000/0826/' > "$@" @tail --lines=+2 "$@".temp >> "$@" What is the purpose of the " @ " at the beginning of the recipe lines? Reading through the GNU Make user's manual I could not find a

问题 I am not aware of any way to define programatically targets in GNU Make. How is this possible? Sometimes one can go away with alternate methods. The ability to define programatically targets in Makefiles is however a very important to write and organise complex production rules with make . Examples of complex production rules are found in the build system of FreeBSD or in Makefile libraries such as BSD Owl The main differences between shell scripts and Makefiles are: In a Makefile, the state