gnu-make

问题 Below is a variable I am using in a makefile. copt = -mcpu=cortex-m3 -mthumb -g -c I want to remove -mthumb and replace it with some other option. Is there any way I can strip the option and add few other options. I know how to add : Example - copt += -O3 but don't know how to remove the already existing options. Thanks! 回答1: $(subst from,to,text) Performs a textual replacement on the text text: each occurrence of from is replaced by to. The result is substituted for the function call. In

问题 Here is a simple Makefile. FILENAME=test.`date +"%Y.%m.%d %H:%M:%S"`.txt test: @echo ${FILENAME} @sleep 2s @echo ${FILENAME} The output of make test is test.2013.02.18 15:30:23.txt test.2013.02.18 15:30:25.txt The problem is that FILENAME is being calculated each time it is used. I want it to be calculated only once and be the same while script is running. Am I doing it wrong? 回答1: GNU Make has two flavours of variables. You have used a recursively-expanded variable, but you want a simply

问题 I have no clue why it doesn't work.. Normally this is supposed to be the easy part, I'm trying to get this fucked up thing to work for days and it still doesn't do anything. Please Help me because I'm very close to throwing this computer through the window. > C:\...\Downloads\crypto50>mingw32-make -f > GNUmakefile process_begin: > CreateProcess(NULL, uname, ...) failed. process_begin: > CreateProcess(NULL, uname, ...) failed. process_begin: > CreateProcess(NULL, uname, ...) failed. g++ -g

问题 Background I have a (large) project A and a (large) project B, such that A depends on B. I would like to have two separate makefiles -- one for project A and one for project B -- for performance and maintainability. Based on the comments to an earlier question, I have decided to entirely rewrite B's makefile such that A's makefile can include it. This will avoid the evils of recursive make: allow parallelism, not remake unnecessarily, improve performance, etc. Current solution I can find the

问题 This is following question. I have Makefile.real ( Makefile from prev question): all: a b a: echo a exit 1 b: echo b start sleep 1 echo b end Now I want to create Makefile that is simple wrap of Makefile.real : It calls make with Makefile.real with the same args as it was called It should print error message id Makefile.real fails This is my goal - print error message in the end of parallel make (see question) Therefore following commands should terminate with error message: make -j1 a b (1)

问题 I split a big file using the split command in a Makefile recipe. trails : $(OBJ) sort -m $? | accumulate.py --threshold 30 | split -C 10MB -d -a 3 - trail. I then rename the resulting files to have the .acc extension. The idea is to have an implicit rule applied on this extension later. The issue I face is that variable expansion happens before the .acc files are generated. For example the following rule doesn't produce anything: all: $(wildcard *.acc) trails @echo $? Using the patsubst

问题 I am trying to build a feature into my makefile which allows me to specify a list of libraries a particular library depends on This will allow dependants of a library to automatically be rebuilt if that library's dependencies are rebuilt, and also have the dependencies added to the link line. I asked a related question on SO here, and working through a given answer, I came up with the following test uniq = $(if $1,$(firstword $1) $(call uniq,$(filter-out $(firstword $1),$1))) expand-deps = $1

问题 I'm writing a Makefile using static pattern rules and I want for each element of TARGETS a variable assigned to the current target name (here the stem '%'). TARGETS = a b c d all : $(TARGETS) $(TARGETS) : % : DIR = % $(TARGETS) : % : %_setup build a_setup : code for a b_setup : code for b ... build code using "DIR = XX" previously configured but gnumake complains about the target-specific variable DIR: make: *** No rule to make target 'DIR', needed by 'a' Is it possible to mix static pattern

问题 How to check from the command line whether GNU Make is built with support of Guile? Inside Makefile it can be determined via analyzing .FEATURES variable (see documentation). 回答1: As @ruvim points out, the manual says You can determine whether GNU Guile support is available by checking the .FEATURES variable for the word guile . $(if $(filter guile,${.FEATURES}) \ ,$(info Guile suppoerted, yay!) \ ,$(error Guile not supported - update your make)) 回答2: One possible way is a quasi makefile in

问题 I'm reading the GNU make manual, and got confused about the variable inheritance mechanism. Let me go through the basics first. I quote from the manual chapter 6.10 Variables from the Environment : Variables in make can come from the environment in which make is run. Every environment variable that make sees when it starts up is transformed into a make variable with the same name and value. So imagine that I open a shell (call it "shell 1") and I define two variables. Then I startup make with