gnu-make

问题 I was reading gnu make section 10.5.4 "How patterns match" and it does not sound like I can do what I want. I want to setup a directory structure where my source code is in one directory, and there are sub-directories to hold object files. One sub-directory for each build configuration. So I might have these files a.c debug/a.o # compiled with -g release/a.o # compiled with -O So I would like to make rules like this debug/%.o : %.c gcc -c -g %.c -o $@ release/%.o : %.c gcc -c -O %.c -o $@ But

问题 I put the function make_color() { make $1 | ccze -A } in .bashrc to get colorized make-output. His works fine, but make s tab-completion for selecting targets is lost. Is there any way to preserve the tab-completion of command in the function, or something else I could do to achieve tab completion and pipe? 回答1: Add this in your ~/.bashrc or run in your local shell: complete -F _make make_color The function name _make may be different in your case. You can get the name using: $ complete -p

问题 I have a set of makefiles I use to build a 'big' C project. I am now trying to reuse some in my C++ project and have run into this headache that I just cannot figure out. The makefile looks like this SOURCES = \ elements/blue.cpp # Dont edit anything below here VPATH = $(addprefix $(SOURCE_DIR)/, $(dir $(SOURCES))) CXXFLAGS = $(OPT_FLAGS) -MMD -MF $(BUILD_DIR)/$*.d -D_LINUX -DNDEBUG -pipe DCXXFLAGS = $(DEBUG_FLAGS) -MMD -MF $(BUILD_DIR)/$*.d -v -D_LINUX -D_DEBUG -pipe OBJECTS := $(patsubst %

问题 var := 'C:/some/path here' labas all: @echo $(words $(var)) This returns 3 . How to make it return 2 ? Or make does not work the way I think?? 回答1: Make definitely doesn't work the way you think, if you think that make has any interest in quotes of any type :). Make ignores (i.e., treats as normal characters like any other) both single- and double-quote characters in virtually every situation, and all make functions work in simple whitespace delimiters without regard to quote characters. In

问题 I have a problem that I just can't wrap my head around. I have a minimal example makefile that is supposed to compile a very simple .c file into an executable program. When I run make , the compiler starts compiling and then produces an error message "T:\printOffsets.c:10:21: error: bootIfc.h: No such file or directory" Then I copy the exact same command line make is using to build the target and run it directly in the same Windows command shell instance, and suddenly compilation succeeds

问题 If my current environment, $ ulimit -s 10240 But if I run a process through gmake, the stack size is unlimited. For instance (the ;: is to make gmake use the shell to execute the command, otherwise it will try to find an executable by that name) $ cat Makefile default: ulimit -s; : $ gmake ulimit -s; : unlimited is it possible to get gmake not changing the limit? if not, is it possible to reset the limit to what I want for all the rules without modifying them (while I may change the main

问题 I have been trying to build glibc on Clear Linux, with a previous issue discussed here: How do I build into a specified directory using the "prefix" option of configure? Now that I have succeeded in running configure, there seems to be something wrong in the makefile: james@clr ~/Downloads/glibc $ make Makeconfig:42: *** missing separator. Stop. line 42 of Makeconfig: objdir must be defined by the build-directory Makefile. and the nakefile up to the point of error: ifneq (,) This makefile

问题 I have two makefiles, directoryA/Makefile and directoryB/Makefile . directoryA/Makefile depends on targets in a rather large and complex directoryB/Makefile . I could do a recursive make $(MAKE) -C directoryB But that is undesirable for several reasons. Two big reasons: I make have to execute the makefile several times, and make can't correctly know when rebuilding a target is necessary. I would like to use the include directive. The problem is twofold: The targets in directoryB/Makefile are

问题 I am trying to write a recursive make recipe. In this recipe, each target is dependent on a file with an equal name on the parent directory. A minimal (non-working) example: foo/.dirstamp: mkdir $(dir $@) touch $@ .SECONDEXPANSION: %/.dirstamp: $$(dir $$*).dirstamp mkdir $(dir $@) touch $@ With this example, I would expect make foo/bar/qux/lol/.dirstamp to generate the whole directory tree (if it does not exist), touching all .dirstamp files along the way. However, it does not work: $ ls #

问题 From the docs: $? The names of all the prerequisites that are newer than the target, with spaces between them. Now, given a makefile: # Create target 'all', that is created later than 'old', which was created after 'older'. $(shell touch older) $(shell sleep 1) $(shell touch old) $(shell sleep 1) $(shell touch all) all : old phony; @echo '"$$?" is: "$?"' # A command to turn the file 'old' even "older", by acquiring the modification-time of 'older'. old :: cp -p 'older' 'old' .PHONY: phony