gnu-make

问题 gcc main.c -o main -I include I am creating a small c application where my all source files are in src directory while all header files in include directory, also all common files are in common directory. All these three directories are under one directory named as "app" directory along with main.c. Now i am trying to run main.c which contains #include directive include header files from include and function calls to .c files in both common and src directories. I am using -I but it is useful

问题 All I am wanting to do something along the lines of... some_file.out : ..... ver_$(basename $@).ver: ..... The $@ does not expand as expected but only in the rule header. Inside the body of the rule all uses of ver_$(basename $@).ver expand as desired. How would I modify this to make it work as desired? 回答1: You have ellipses eliding too many important parts of your example to provide a full solution. However, one option is to use static pattern rules, like this: some_file.out : %.out : ver_%

问题 I have the following rules in my Makefile: %.o: $(HFILES) %.o: %.c $(CC) $(CFLAGS) $*.c where HFILES contains all headers of my project. The Problem is that this does not rebuild the object files when a header changes as intended. Why does the first line not add the headers to the prerequisites of the object files? 回答1: Because that's not how pattern rules work. The documentation for pattern rules says that when you create a pattern rule with no recipe that cancels the pattern rule (that is,

问题 I'm trying to do something pretty simple in compiling .c and .cpp files to create an application on Ubuntu. I created a Makefile but it fails with the following error. ~/code/test$ make gcc -Wall -c test1.c -o test1.o g++ -c -Wall -D__STDC_LIMIT_MACROS main.cpp -o main.o g++ -c -Wall -D__STDC_LIMIT_MACROS class_a.cpp -o class_a.o echo g++ test1.o main.o class_a.o -o myapp g++ test1.o main.o class_a.o -o myapp g++ test1.o main.o class_a.o -o myapp main.o: In function `main': main.cpp:(.text

问题 I am searching for a command, that separates all given parameters with a specific delimiter, and outputs them quoted. Example (delimiter is set to be a colon : ): somecommand "this is" "a" test should output "this is":"a":"test" I'm aware that the shell interprets the "" quotes before passing the parameters to the command. So what the command should actually do is to print out every given parameter in quotes and separate all these with a colon. I'm also not seeking for a bash-only solution,

问题 I would like do something like following. I would like to have a variable argument list for a Makefile. make VAR_ARG_LIST=src1,src2,src3,src4 Can I do like this? If I can, how do I extract src1,src2 or src3 from the variable VAR_ARG_LIST inside the Makefile? Thanks, 回答1: You really haven't provided enough information for a solution. Why do you want to extract those values? What do you want to do with them? However, I can answer the question you asked and hope it is useful. If you're using GNU

问题 Say I have a list of source files like this: SOURCE=aaa.src bbb.src ccc.src I want to create a rule to build each corresponding target in its own folder, the name of which depends on the soruce file. Sourcefile ----> Corresponding output file / target aaa.src -------------------> aaa/aaa.out bbb.src -------------------> bbb/bbb.out ccc.src -------------------> ccc/ccc.out How do I write a rule for this using GNUMake? My best effort was the following Makefile: .PHONY: all clean CC=somecompiler

问题 Update: GNU Make 3.81, Ubuntu 12.04 I have a set of markdown files that I want to compile to (say) html files, so this is my rule: %.html: %.md pandoc $< -o $@ So make foo.html would convert foo.md into foo.html . However, there are spaces in the source markdown filenames and I do not have the ability to control these , that is I can't change a setting to remove the spaces. This means if I make foo\ bar.html , I get make: *** No rule to make target `foo bar.html'. Stop. How can I write a

问题 What I have: I have a non-recursive makefile which searches for module.mk files, and includes them modules := $(shell find . -name module.mk) include $(modules) If I want to create a static library , the module.mk looks like this: $(eval $(call make-lib, test_lib)) Which will find a list of all .cpp files in the current directory, and call do-make-lib , with: $1 being the library name $2 being the list of source files do-make-lib is defined as follows (some details omitted for brevity):

问题 I have a data file that is processed by a script to produce multiple output files. Each of these output files is then processed further. Which files are created depends on the contents of the input file, so I can't list them explicitly. I can't quite figure out how to refer to the various files that are generated in a makefile. Currently, I have something like this: final.out: *.out2 merge_files final.out $(sort $^) %.out2: %.out1 convert_files $? %.out1: data.in extract_data data.in This