gnu-make

问题 I have a number of armcc commands, which I like to translate to gcc options. The code was originally for a different environment. I did look at gcc --help and I did not see the same options such as --cpu. Can anyone help please? Here are the commands: del .\obj\*.o armcc -c --debug --cpu=Cortex-A9.no_neon.no_vfp -O1 -o ./obj/foo ./src/foo.c armcc -c --debug --cpu=Cortex-A9.no_neon.no_vfp -O1 -o ./obj/bar ./src/bar.c armasm --debug --cpu=Cortex-A9.no_neon.no_vfp -o ./obj/buz.o ./src/buz.s

问题 I am trying to make a makefile, which can make an exe for CppUTest. It can not find the headers, what have I done wrong? First time making a makefile, not 100% sure what I'm doing. #The compiler to use CC = g++ LINK = -g -pedantic -Wall -lstdc++ -lpthread -ldl -lm -Wl,-rpath,. COMPILE = -g -O3 -D_THREAD_SAFE -pedantic -Wall -c -Wno-deprecated #Name of the EXE file to create. EXE = ./Tests SRCS = $(shell ls *.cpp) OBJS = $(subst .cpp,.o,$(SRCS)) #Extra flags to give to the C compiler. CFLAGS =

问题 In a GNU Makefile , there are two types of variables: # simple variable (immediate evaluation): VAR := some_assignment # recursively expanded variable (deferred evaluation): VAR = some_assignment One may append to a recursively expanded variable using: IMMEDIATE += DEFERRED or IMMEDIATE For the append operator, '+=', the right-hand side is considered immediate if the variable was previously set as a simple variable (':=' or '::='), and deferred otherwise. Is there any way to prepend to a

问题 Imagine a directory tree (which might be more than one level deep) containing several Markdown files. A PDF version of each file exist in the same directory and must be updated each time the corresponding Markdown file is updated. What rule must be written in a single Makefile in the root directory of this tree to achieve this? I am looking a for a solution where files can be added or removed from the directory tree without a need for updating the Makefile. Assumptions: all markdown files

问题 I'm trying to create a Makefile using a monorepo and am struggling a bit with dynamic output directories based on the source files' directories. My project is laid out like so: % tree . . ├── Makefile └── packages ├── bar │ └── src │ └── index.js │ └── other-file.js └── foo └── src └── index.js 5 directories, 4 files I want to process each *.js file inside of each package (e.g., ./packages/foo/src/index.js ) and emit the output into another directory (specifically, ./packages/foo/lib/index.js

问题 I am using a Makefile and GNU make to create various document output targets based on a source Markdown file. This includes using latex or pdflatex to create a DVI file. Use of images in other than EPS or PS formats causes errors. I can search-and-replace image names within the source markdown file, and have done so. What I'd like to do is create a makefile rule for all image files in the images/ subdirectory, and to run convert to create eps versions of those files. So: images/myimage1.png

问题 This question is similar in spirit to question 2543127. I have a gnu makefile with a list of header files. Each header file may be located in a different directory, e.g., HEADERS = $(wildcard *.h) $(wildcard foo/*.h) $(wildcard bar/*.h) and I want to have the makefile copy all headers to an include directory INCDIR = ../include and when a dummy target, e.g., ALL is invoked, it will update the header files in the include directory appropriately, i.e., .PHONY: ALL ALL : $(addprefix $(INCDIR)/,$

问题 Here's a skeleton Makefile just to make it easier to describe the problem: all_tests : unit_tests other_tests_1 other_tests_2 ... other_tests_N unit_tests : set1_summary.txt set2_summary.txt ... setN_summary.txt %_summary.txt : %_details.txt perl createSummary.pl --in $^ -out $@ %_details.txt : test_harness ./test_harness --test-set $* So I have a test runner that produces a file with detailed results, and then a filtering mechanism to create a summary file. Now, the test runner application

问题 I got the following Makefile with several compilers, and I would like to invoke them in a loop through the variable cc: cc_x64=x86_64-linux-gnu-gcc cc_mips=mips-linux-gnu-gcc all: for arch in "x64" "mips" ; do\ cc="cc_$$arch";\ $($(cc)) some_file -o some_bin By $($(cc)), I am trying to substitute $(cc) with cc_xxx, and in turn, substitute it with the actual command I am trying to execute. This is called a computed variable name in GNU Make's documentation: https://www.gnu.org/software/make

问题 Now to proceed further I need to change the presentation of existing Makefile. Presently I am using: ~/Linuz/src: 1.c, 2.c, 3.c ... ~/Linuz/inc: abc.h, xyz.h and makefile is in: ~/Linuz/some_other_dir/ But need to change the structure. Want to create a library from ( ~/Linuz/src/ and ~/linuz/inc ) Library will be used to get executable. Application source files(.c files) are in ~/Linuz/app/ ~/Linuz/bin/ should be created during compilation to store all the object files and executable file.