gnu-make

问题 I want the rules of a target to be executed but all dependent targets shall regard this target as satisfied. How can I achieve this? Example: $(NETWORK_SHARE)/foo.log: @echo Warning: server offline, still continue ... @exit 0 foo.csv: $(NETWORK_SHARE)/foo.log @echo Long export from a (different) server @echo sleep 20 @echo foo > $@ If $(NETWORK_SHARE)/foo.log exists: foo.csv shall be rebuilt if $(NETWORK_SHARE)/foo.log is newer than foo.csv; otherwise nothing should happen (default) If $

问题 UPDATED PROGRESS I am sorry I forgot to specify this question as an Arduino question. I just assumed that it's a preprocessor problem which is kind of independent of what platform this is being executed on. I am using Arduino-Make and I am trying to pass in USERNAME and PASSWORD BOARD_TAG = mega2560 CPPFLAGS = -DUSERNAME="$(USERNAME)" -DPASSWORD="$(PASSWORD)" include $(ARDMK_DIR)/Arduino.mk Command line: make USERNAME="HELLO" PASSWORD="WORLD" Code: void setup() { Serial.begin(9600); String

问题 I have a set of C source files that need to be built in a shared lib and in an executable, with different CFLAGS: %.o: %.c $(CC) -c -o $@ $^ $(BIN_CFLAGS) lib-%.o: %.c $(CC) -c -o $@ $^ $(LIB_CFLAGS) Make says: No rule to make target 'lib-x.o', needed by 'liby.so'. Stop. Is there no alternative to writing the rules for lib-x.o and the other object files one by one ? 来源： https://stackoverflow.com/questions/55724483/build-multiple-objects-from-one-source-file

问题 I am new in GCC and I am wondering how to tell the compiler that several include directories need to be specified as default for searching .h files. I read that -I dir is the key to accomplish that but doing my makefiles I encounter some problems. For example: include_dir = C:/Users/rmrd001/Documents/Make/GCC/first/mydir/ FLAGS = -I "$(include_dir)" func2.o: func2.c func2.h gcc $(FLAGS) -c func2.c And I got the error: make:*** No rule to make target 'func2.c', needed by 'func2.o'. Stop. The

问题 I have a makefile with a recursive call to itself. When I first run make, the object files are created and linked just fine. But when I modify a source file and run make again, the objects are not recreated (make says the target is up to date). I need to run make clean and then run make. Here is simplified version of my makefile which I think includes all relevant information: PCC = mpicc #Locations OBJDIR = ./objects #Compiler and linker flags FLAGS = -g -lm #Object files SHAREDOBJS = $

问题 In order invoke my Makefile from different locations without messing up relative paths, I reference paths using a Makefile variable as given in another answer: DIR=$(shell dirname $(realpath $(lastword $(MAKEFILE_LIST)))) I get that MAKEFILE_LIST differs when I include other files, but since I store its value in a variable before making any includes, I am surprised that the variable value differs. Example: $ tree . . ├── another_file └── subdirectory └── Makefile $ cat Makefile DIR=$(shell

问题 In my makefile I have: all: for i in {20..50000..10} ; do \ echo "Computing $$i" ;\ done Which should print numbers 20, 30, 40, ..., 50000 each on a separate line. This works under Debian oldstable (GNU Make 4.0, GNU Bash 4.3), but not Debian stable (GNU Make 4.1 and GNU Bash 4.4.12). Debian stable prints just the string "{20..50000..10}". Why is this? What is the portable way to write this for loop in a makefile? 回答1: Stick with a POSIX-compatible loop: all: i=20; while [ "$$i" -le 50000 ];

问题 I am trying to create a directory inside target based on a rule but for some reason the variable is not getting expanded i.e., $(OUT_DIR) is blank and mkdir -p does not work. Here is the code target_%: /home/user/%/.file : file.c export OUT_DIR = /home/user/$* ; \ mkdir -p $(OUT_DIR) ;\ . . . After making the changes suggested by @Beta, here is how the code looks like target_%: /home/user/%/.file : file.c export OUT_DIR=/home/user/$* ; \ mkdir -p $${OUT_DIR} ;\ cd $${OUT_DIR} ; \ ln -s /home

问题 I've the following code inside make file which gets from command array of strings apps := $(shell fxt run apps) go: @for v in $(apps) ; do \ echo inside recipe loop with sh command: $$v ; \ done The command returns array like [app1 app2 appN] (could be many apps inside) But I need it to be app1 app2 appN , any idea how to remove the array [] ? when I run make I got the following inside recipe loop with sh command: [app inside recipe loop with sh command: app2] 回答1: You simple can use subst

问题 (this is similar to GNU make: Execute target but take dependency from file but slightly different). When I try to force to build a target, make automatically thinks that this target is out of date and forces a run of all targets which depend on it. In my case, the target is a recursive make call which does a lot of work and might just return with "nothing to be done": .PHONY: intermediate.dat intermediate.dat: $(MAKE) expensive_chain_which_finally_creates_intermediate.dat step1.dat: