gnu-make

问题 I have a question regarding the behavior of Make when running targets that are dependent on generated files. Given the source tree and Makefile below, when I run this it takes two runs to complete the "build" even though everything was generated on the first run. $ ls -R .: bar foo Makefile Makefile all: foobar work: mkdir -p work work/foo: work foo cp foo work/foo work/bar: work bar cp bar work/bar foobar: work/foo work/bar make $ make mkdir -p work cp foo work/foo cp bar work/bar $ ls -R .:

问题 I have a makefile snippet: all: $(objects) fresh: clean all clean: ;rm $(objects) Here, I want to ensure that when I do make fresh - clean should precede all . But how can I make sure this, given that when I do make all , clean should not be made? I can imagine that one way could be like this fresh: clean make all Is it the right (or the only) way to solve this issue? 回答1: If you use GNU make: all: @echo $@ @sleep 1 @echo end $@ clean: @echo $@ @sleep 1 @echo end $@ fresh:: clean fresh:: all

问题 The GNU make manual does not excel at explaining this part, I could not find the explanation or I could not infer the information elsewhere. I realize % is a kind of wildcard, but what is the difference between % and * in the context of targets , dependencies and commands ? Where can I use it and does it have the same meaning everywhere? target: dependencies ... commands 回答1: The wildcard character * is used to simply generate a list of matching files in the current directory. The pattern

问题 So, I have the following code: OBJ := $(addprefix 'obj_', $(basename $(notdir /build/common.mk))) so now OBJ1 is "obj_common" ifeq ($(OBJ),obj_common) @echo equal (**don't know how to format indent in this website..assume there is.**) endif the ifeq can't compare $(OBJ) to obj_common, at least it didn't echo... (However, if I get rid of addprefix function as follow:) OBJ := $(basename $(notdir /build/common.mk)) so now OBJ1 is "common" ifeq ($(OBJ),common) @echo equal endif this code would

问题 Perhaps it's something that I'm getting wrong. Basically my task is to use make to automate a build, deploy, starting, stopping of different services. One of the things that I'm trying to do is to have a variable as a target prerequisite, however that variable has to be changed in another target. Here's a basic sample of what I'm trying to do: IMAGE_COUNT=-1 count_images: $(eval IMAGE_COUNT=5) _should_build: $(if $(findstring $(IMAGE_COUNT),0), build,) build: ...some procedure to build...

问题 I have a makefile with some targets (say data1 through dataN , on which alldata depends) that generate some data, and a prettify target which iterates over the output and creates a pretty report. (note: there are lots of dataN targets and the makefile is machine-generated) Some of the dataX targets occasionally fail, but I would like to run prettify anyway, so prettify doesn't depend on alldata . Is there a way to run the equivalent of make -k alldata || make prettify in a single invocation

问题 I am searching a make like build tool that supports (besides usual make features): Automatic deletion of temporary created files (like in GNU make for example) Regular expressions in rule patterns (like e.g. in Cook About 1: By default GNU make deletes temporary files. For example have these rules: %.c: %.y some-comand %.o: %.c some-comand If you have a file foo.y and call make foo.o then make derives that is has to create first foo.c and then foo.o. After it is ready it delete the temporary

问题 I have a makefile that has C INCLUDES with spaces in them. There is no way for me to get around having to have the spaces in the file names. Is there any way to have spaces in file names with gnu make? 回答1: Make has some basic support for this by escaping spaces in filenames, in that the following Makefile will correctly compile and recompile the C file foo bar.c : foo\ bar: foo\ bar.c gcc -o "${@}" "${<}" However, you have to be super-careful in quoting every command you run, and variables

问题 I'm trying to compile Atmel's Bitcloud (WSNDemo) on Ubuntu 14.04. The makefile (http://pastebin.com/4gGcGRvY) however seems not executing a rule on my computer. The problem is that it doesn't start the compiler only the linker. And of course the linker then can't find the objects. $(OBJ_PATH)/%.o: $(SRCS) is never called (line 187 in makefile) upon running this: make -n -f Makefile_All_StdlinkSec_MegaRf_Atmega2564rfr2_16Mhz_Gcc all APP_NAME=WSNDemo However if I specify the object and also the

问题 I am programming for a big project, so I cooperate with others. To make the directory easily managed, my directory is like below: project: --include (header files from others supplied for me) --lib (libraries from others supplied for me) --L3_CVS (this folder include all my files) -- Makefile -- sourceFile (all my source files here) -- include_private(all header files used only by myself) -- appl (all my C files here) if I want to include a .h file in my .c file, do I need to write in .c file