gnu-make

问题 How and when do I quote a string in a make file? What is best practice? Is the following the way to quote? $(warning $(shell ls -ld "$(CURDIR)" ) ) I'm familiar with Bash where you usually quote variables to allow for embedded spaces. Do you do such in a makefile? How should I do assignment statements with a string? vara := "$(CURDIR)" varb := $(CURDIR) varc := /home/me/source vard := "/home/me/source" What about the space after the equal? 回答1: You should never quote anything because of make

问题 So I followed the Advanced Auto-Dependency Generation paper -- Makefile : SRCS := main.c foo.c main: main.o foo.o %.o: %.c $(CC) -MMD -MG -MT '$@ $*.d' -c $< -o $@ cp $*.d $*.tmp sed -e 's;#.*;;' -e 's;^[^:]*: *;;' -e 's; *\\$$;;' \ -e '/^$$/d' -e 's;$$; :;' < $*.tmp >> $*.d rm $*.tmp clean:: -rm *.o *.d main -include $(SRCS:.c=.d) main.c : #include "foo.h" int main(int argc, char** argv) { foo() ; return 0 ; } foo.h : #ifndef __FOO_H__ #define __FOO_H__ void foo() ; #endif -- and it works

问题 I'm trying to create a Makefile which places my .o files in a different directory than my source files. I'm trying to use a pattern rule so I don't have to create identical rules for each source & object file. My project structure looks something like: project/ + Makefile + src/ + main.cpp + video.cpp + Debug/ + src/ [contents built via Makefile:] + main.o + video.o My Makefile looks something like: OBJDIR_DEBUG = Debug OBJ_DEBUG = $(OBJDIR_DEBUG)/src/main.o $(OBJDIR_DEBUG)/src/video.o all: $

问题 I have a project which includes a code generator which generates several .c and .h files from one input file with just one invocation of the code generator. I have a rule which has the .c and .h files as multiple targets, the input file as the prerequisite, and the recipe is the invocation of the code generator. I then have further rules to compile and link the generated .c files. This works fine with a -j factor of 1, but if I increase the j factor, I find I get multiple invocations of the

问题 I'm using UnitTest++ to allow me to create unit tests for some C++ code (that should build on Linux or Mac OS X). I have a directory structure like this: src - Foo.cpp - Bar.cpp test - FooTest.cpp - BarTest.cpp - Main.cpp - Makefile UnitTest++ - libUnitTest++.a And this Makefile (adapted from the UnitTest++ Makefile) works nicely (with GNU make): test = TestFooAndBar src = ../src/Foo.cpp \ ../src/Bar.cpp test_src = Main.cpp \ FooTest.cpp \ BarTest.cpp lib = ../UnitTest++/libUnitTest++.a

问题 What does the following do in a Makefile? rule: $(deps) @: I can't seem to find this in the make manual. 回答1: It means "don't echo this command on the output." So this rule is saying "execute the shell command : and don't echo the output. Of course the shell command : is a no-op, so this is saying "do nothing, and don't tell." Why? The trick here is that you've got an obscure combination of two different syntaxes. The make(1) syntax is the use of an action starting with @, which is simply not

问题 How can I compact the folllowing Makefile targets? $(GRAPHDIR)/Complex.png: $(GRAPHDIR)/Complex.dot dot $(GRAPHDIR)/Complex.dot -Tpng -o $(GRAPHDIR)/Complex.png $(GRAPHDIR)/Simple.png: $(GRAPHDIR)/Simple.dot dot $(GRAPHDIR)/Simple.dot -Tpng -o $(GRAPHDIR)/Simple.png $(GRAPHDIR)/IFileReader.png: $(GRAPHDIR)/IFileReader.dot dot $(GRAPHDIR)/IFileReader.dot -Tpng -o $(GRAPHDIR)/IFileReader.png $(GRAPHDIR)/McCabe-linear.png: $(GRAPHDIR)/McCabe-linear.dot dot $(GRAPHDIR)/McCabe-linear.dot -Tpng -o

问题 I've makefile which looks like follows apps = app1 app2 app3 all: dir app1 app2 app3 zip cleanup Now I want to do some loop on the list of apps varible, something like `loop on apps endloop` Is it possible in makefile to loop on it, I need to do loop on apps varible list update lets say this variable( apps ) is generated by my program in the make file, which provide for each project diffrent values of apps, sometimes its apps= app1 app2 sometimes its apps= app1 and sometimes can be 20 apps or

问题 I find myself a little torn between two possibilities to declare GNU make tragets phony in Makefiles. One is declaring all phonies in one go: .PHONY: targ1 targ2 targ3 targ1: ... targ2: ... targ3: ... Which has the advantage of being more readable (to me) and more tidy. But one can't see quickly which targets are phony. The other possibility is declaring the phoniness along with the rule (directly in front or behind): .PHONY: targ1 targ1: ... .PHONY: targ2 targ2: ... targ3: ... .PHONY: targ3

问题 I have written a makefile like this: HEADER = -I./cygdrive/c/cpros/kajj/source4 LIBB = -L./cygdrive/c/cpros/kajj/source1 -L./cygdrive/c/cpros/kajj/source2 LIBRA = -larith -ldekk target : game.o gcc $(HEADER) $(LIBB) $< -o $@ $(LIBRA) game.o : game.c gcc -c game.c I have created my own static library and included the header file path and library path. When I execute my makefile it gives an error saying that /usr/lib/gcc cannot find -larith -ldekk . It is pointing to the lib/ directory but it