gnu-make

问题 I have a makefile rule in while I am executing a linux tool. I need to check the exit status of the tool command, and if that command fails the make has to be aborted. I tried checking with $?, $$? \$? etc in the makefile. But they gives me syntax error when makefile runs. What is the right way to do this ? Here is the relevant rule in Makefile mycommand \ if [ $$? -ne 0 ]; \ then \ echo "mycommand failed"; \ false; \ fi 回答1: In the makefile-: mycommand || (echo "mycommand failed $$?"; exit 1

问题 I have already seen How to manually call another target from a make target?, but my question is a bit different; consider this example (note, stackoverflow.com changes the tabs to spaces in display; but tabs are preserved in source, if you try to edit): TEXENGINE=pdflatex pdflatex: echo the engine is $(TEXENGINE) lualatex: TEXENGINE=lualatex echo Here I want to call the pdflatex rule, to check $(TEXENGINE) there! Here, if I run the default target ( pdflatex ), I get the expected output: $

问题 I installed MinGW and MSYS, added C:\MinGW\bin to PATH but I still can't run Makefile on Windows' cmd . I would like to run cmd.exe and there type, for example, make all but my cmd says that there is no such command. What should I do? I don't want to use MSYS shell, that's not the point. Any ideas how to use GNU Make in Windows cmd as I can do it in Ubuntu? I'm not interested in Cygwin . 回答1: Here's how I got it to work: copy c:\MinGW\bin\mingw32-make.exe c:\MinGW\bin\make.exe Then I am able

问题 Compiling the Box2d Tesbed is supposed to be simple: from iforce2d: Download the Box2D source code archive from here. If you want to use the terminal all the way, you could also do this (if wget is not available, use yum to install it): wget http://box2d.googlecode.com/files/Box2D_v2.1.2.zip Use the following commands to unzip and build it. [...] unzip Box2D_v2.1.2.zip cd Box2D_v2.1.2/Box2D/Build cmake .. make ( These instructions are pretty old, I did get my source with git clone https:/

问题 I have a C++ small project using GNU Make. I'd like to be able to turn the following source files: src/ a.cpp b/ b.cpp c/ c.cpp into the following output structure (I'm not concerned about duplicates at this point): build/ a.o b.o c.o So far I have the following, which unfortunately puts the .o and .d right next to each .cpp: OBJS := $(foreach file,$(SRCS),$(file).o) DEPS := $(patsubst %.o,%.d,$(OBJS)) sinclude $(DEPS) $(OBJS) : %.o : %.cpp @echo Compiling $< $(CC) $(CC_FLAGS) $(INCS) -MMD -o

问题 Shell commands sometimes take a long time to run, so you may not want to do VAR = $(shell slow-cmd) (with = , the slow-cmd will be run every time the variable is referenced). Using VAR := $(shell slow-cmd) can be useful, but if you are building a target that does not ever need the variable expanded, you will get one more invocation of the slow-cmd than is needed. In the following makefile (with gnu-make), you can get the desired behavior: the shell command to define a value for V2 is never

问题 I have following Makefile, and I would like to configure it to produce debug build by default and release build by specifying corresponding target. The problem I am trying to solve right now is following, - project contains unit tests, and I want them to be included in default build, but excluded from release, so I am added release target to Makefile: FC = ifort FFLAGS = -c -free -module modules -g3 -warn all -warn nounused LDFLAGS = -save-temps -dynamiclib INTERFACES = src/Foundation.f units

问题 I've got a slightly hackish makefile for running tests: ### Run the tests tests := tests/test1 tests/test2 ... test: $(tests) $(tests): %: %.c gcc -o $@ $(testflags) $< $@ It works, but it makes Make do something I've never seen it do before. My test is currently broken, and causes a bus error. Make gives the following output: gcc -o tests/test1 [flags blah blah] tests/test1.c tests/test1 make: *** [tests/test1] Bus error make: *** Deleting file `tests/test1' I'm curious about the last line.

问题 I'm reading Managing Projects with GNU Make, and found this example in Chapter 2.7 - Automatic Dependency Generation. The Author says their from the GNU manual: %.d: %c $(CC) -M $(CPPFLAGS $< > $@.$$$$; \ sed s',\($*\)\.o[ :]*,\1.o $@ : ,g' < $@.$$$$ > $@; \ rm -f $@.$$$$ However, I was able to do the same thing with this (note the sed ): -include $(subst .c,.d,$(SOURCES)) %.d: %.c @$(CC) -M $(CPPFLAGS) $< | sed 's|:| $*.d : |' > $@; All these lines do is generate the dependencies, then add

问题 I've a lot of C files, some have a header (.h), some files not. Here's my makefile : .SUFFIXES: SRC := $(wildard ./src/*.c) OBJ := $(SRC:%.c=%.o) all: $(OBJ) %.o: %.c $(MyNotGCCCompiler) "@../$(*F).cmd" It works fine except that if I change a header file, the target isn't recompiled because not included in the dependencies. How can I manage this case? Thanks 回答1: The standard approach is to generate header dependencies automatically while compiling. For the first compilation no dependencies