gnu-make

问题 I am trying to get the target_compile to work. copy_shared_object: cp shared_object.so ${CURRENT_DIR} PROJECT_SIM_OPTS += -LDFLAGS -L${CURRENT_DIR},-lm -load target_compile: copy_shared_object actual_compile_with_sim_opts . . . actual_compile_with_sim_opts: . . . I am getting the Error despite the fact that I have not added ;\ on the first line starting with cp make: PROJECT_SIM_OPTS: Command not found makefile:282: recipe for target 'copy_shared_object' failed make: *** [copy_shared_object]

问题 I am trying to get the target_compile to work. copy_shared_object: cp shared_object.so ${CURRENT_DIR} PROJECT_SIM_OPTS += -LDFLAGS -L${CURRENT_DIR},-lm -load target_compile: copy_shared_object actual_compile_with_sim_opts . . . actual_compile_with_sim_opts: . . . I am getting the Error despite the fact that I have not added ;\ on the first line starting with cp make: PROJECT_SIM_OPTS: Command not found makefile:282: recipe for target 'copy_shared_object' failed make: *** [copy_shared_object]

问题 I have the following in my makefile. Its a GNUmakefile , so the additional make features are supported: # Undefined Behavior Sanitzier (Clang and G++) ifeq ($(findstring ubsan,$(MAKECMDGOALS)),ubsan) CXXFLAGS += -fsanitize=undefined MAKECMDGOALS := $(subst ubsan,,$(MAKECMDGOALS)) endif # UBsan Running it results in: make ubsan make: *** No rule to make target 'ubsan'. Stop. I know the code path is being executed (by introducing an error in the block). How do I remove the target from the

问题 I have the following in my makefile. Its a GNUmakefile , so the additional make features are supported: # Undefined Behavior Sanitzier (Clang and G++) ifeq ($(findstring ubsan,$(MAKECMDGOALS)),ubsan) CXXFLAGS += -fsanitize=undefined MAKECMDGOALS := $(subst ubsan,,$(MAKECMDGOALS)) endif # UBsan Running it results in: make ubsan make: *** No rule to make target 'ubsan'. Stop. I know the code path is being executed (by introducing an error in the block). How do I remove the target from the

问题 I would like to use a single Makefile to generate targets in hundreds of subdirectories. Each subdirectory is a date/time stamp like this: 20120119_153957 , which matches the following pattern ????????_?????? . There are no other subdirectories that match this pattern. One target I would like to generate is called ????????_??????/graph.pdf . I have a script called make_graph that will make the graph given the subdirectory name. But I'm not sure how to write a Makefile that will automatically

问题 Although both names will do the job, what is the correct name for makefiles? GNU `make' homepage uses Makefile , and I guess it is the good way to name it. Any reasons for typing the front M in upper case ? 回答1: What Name to Give Your Makefile chapter of GNU Make manual clarifies it: By default, when make looks for the makefile, it tries the following names, in order: GNUmakefile , makefile and Makefile . Normally you should call your makefile either makefile or Makefile . ( We recommend

问题 This question already has answers here : Make error: missing separator (12 answers) Closed 2 months ago . For the following make file copied below, I am getting the missing separator error. Nothing seems to be wrong with the tabspace. OBJS = driver.o snapshot.o SHOBJS = malloc.o mymemory.o CC = g++ DEBUG = -g CFLAGS = -Wall -c $(DEBUG) LFLAGS = -Wall $(DEBUG) Snapshot: $(OBJS) $(CC) $(LFLAGS) $(OBJS) -o Snapshot driver.o: snapshot.h driver.cpp $(CC) $(CFLAGS) driver.cpp snapshot.o: mymemory.h

问题 (edit: question more accurate based on @Michael feedback) In bash, I often use parameter expansion: the following commands print " default value " when $VARNAME is unset, otherwise it prints the VARNAME content. echo ${VARNAME:-default value} #if VARNAME empty => print "default value" echo ${VARNAME-default value} #if VARNAME empty => print "" (VARNAME string) I did not find a similar feature on GNU make . I finally wrote in my Makefile : VARNAME ?= "default value" all: echo ${VARNAME} But I

问题 What setup works for GNU make parallel jobs (-j) on Windows? I have tried setting the shell to cmd.exe using MinGW make 3.81, this works in creating the multiple processes but make fails with the "waiting for job" message. Can this work and what is the best setup? (MinGW / Cygwin / ???) Can someone point me to a working example to test against? 回答1: I've never had any promblems using make -jn under Cygwin. It works rather well. I regularly use it with Microsoft's cl.exe compiler. It just

问题 How do I make this work? It errors out with "make: somevariable: Command not found" sometarget: somevariable = somevalue Full example: CXXFLAGS = -I/usr/include/test -shared -fPIC OBJ = main.o Server.o blabla : $(OBJ) ifeq ($(argsexec),true) # Creates an executable CXXFLAGS = -I/usr/include/test $(CXX) -o blabla $(OBJ) $(CXXFLAGS) else # Creates a library DESTDIR = /home/pc $(CXX) -o blabla $(OBJ) $(CXXFLAGS) ./bn.sh endif 回答1: I found a solution using the eval function: $(eval variablename