gnu-make

CMake and Make need to be run twice in order to build code successfully

天大地大妈咪最大 提交于 2019-12-21 17:08:45
问题 I am using CMake 3.8.2, GNU make 4.2.1 and GCC 6.4.0 for my C++14 project and I noticed a strange behavior when building. I am using CMake for an out-of-source build in a sub-folder called "build" where I run cmake .. followed by make . CMake runs fine without any errors and make will build all source files like I expect until it is done compiling and starts linking them. It will then fail with an error [ 83%] ... [100%] Linking CXX executable myproject /usr/bin/ld: some-source-file.cc.o:

Properly build a git submodule with gnu make

巧了我就是萌 提交于 2019-12-21 16:16:20
问题 I currently try to write a Makefile that build properly a project which contains a git submodule. This submodule have its own set of makefiles and produce several targets at once, including some libraries. This Makefile should have the following properties. Don't rebuild twice the submodule even with parallel build. Update the submodule targets when the submodule code has changed (maybe because I navigated through the revisions of the main repository). Re-link the main project when the

depending on directories in make [duplicate]

筅森魡賤 提交于 2019-12-21 09:03:16
问题 This question already has answers here : how to prevent “directory already exists error” in a makefile when using mkdir (12 answers) Closed 6 years ago . This is a followup to my earlier question: SO 4403861 because the suggested solutions broke the dependencies, making the makefile useless. I can't figure out why. I am using gnu make 3.82 I have a rule that works if the obj directory has been created: objdir:=../obj $(objdir)/%.o: %.C $(COMPILE) -MM -MT$(objdir)/$(notdir $@) $< -o $(DEPDIR)/

depending on directories in make [duplicate]

感情迁移 提交于 2019-12-21 09:03:06
问题 This question already has answers here : how to prevent “directory already exists error” in a makefile when using mkdir (12 answers) Closed 6 years ago . This is a followup to my earlier question: SO 4403861 because the suggested solutions broke the dependencies, making the makefile useless. I can't figure out why. I am using gnu make 3.82 I have a rule that works if the obj directory has been created: objdir:=../obj $(objdir)/%.o: %.C $(COMPILE) -MM -MT$(objdir)/$(notdir $@) $< -o $(DEPDIR)/

file was built for unsupported file format which is not the architecture being linked (x86_64)

浪子不回头ぞ 提交于 2019-12-21 04:43:16
问题 I have a build file on OSX Lion VPATH = src include CFLAGS ="-I include -std=gnu99" hello: hello.o gcc $^ -o $@ hello.o: hello.h hello.c gcc $(CFLAGS) -c $< -o $@ But when I try and run this make file I get the following error ld: warning: ignoring file hello.o, file was built for unsupported file format which is not the architecture being linked (x86_64) Undefined symbols for architecture x86_64: "_main", referenced from: start in crt1.10.6.o ld: symbol(s) not found for architecture x86_64

Proper method for wildcard targets in GNU Make

不想你离开。 提交于 2019-12-21 03:34:42
问题 I am trying to write a Makefile with my source and object files separated and I can't seem to figure out the proper way to accomplish this. I have two methods that work but I'm hoping someone can point the "correct" way to do this is. My project is separated into a src and obj folder with the Makefile at the same level as these. The first method uses the wildcard function to find the source files in src then uses text replacement to determine the corresponding object files. SRC = $(wildcard

gmake compile all files in a directory

大憨熊 提交于 2019-12-20 12:14:51
问题 we have some C++ code that we need to create a make file in. Each .h and .C pair create an object and then some objects are linked together to form a executable. Pretty standard stuff. This non-gnu make command just builds all the files into object in a directory %.o:%.C $(CC) $(CPFLAGS) -c $< What this does is for each %.C file (ie every .C file) build a corresponding .o file. Does anybody know how to do this with gmake? Cheers Mark 回答1: The syntax you've shown is called a pattern rule in

Can GNU make execute a rule whenever an error occurs?

寵の児 提交于 2019-12-20 11:48:33
问题 This is slightly different from Can a Makefile execute code ONLY when an error has occurred?. I'd like a rule or special target that is made whenever an error occurs (independent of the given target; without changing the rule for every target as the other answer seems to imply with the || operator). In dmake there is special target .ERROR that is executed whenever an error condition is detected . Is there a similar thing with GNU make? (I'm still using GNU make 3.81, but I didn't find

How do I split a string in make?

大兔子大兔子 提交于 2019-12-20 11:07:24
问题 I need to take a parameter in my Makefile that consists of a host identifier in the form host[:port] where the colon and port are optional. So all of the following are valid: foo.example.com ssl.example.com:443 localhost:5000 etc. I want to split the string on the optional colon and assign the values to variables, so that HOST contains foo.example.com , ssl.example.com , localhost , etc., and PORT contains 80 (the default port), 443, and 500 respectively. 回答1: # Retrieves a host part of the

ldconfig error: is not a symbolic link

大城市里の小女人 提交于 2019-12-20 08:56:29
问题 When running: sudo /sbin/ldconfig the following error appears: /sbin/ldconfig: /usr/local/lib/ is not a symbolic link When I run file: file /usr/local/lib/ /usr/local/lib/: directory Inside /usr/local/lib/ there are three libraries that I use. I'll call them here as lib1 , lib2 and lib3 . Now, when I do an ldd on my binary it results: lib1.so => not found lib2.so => not found lib3.so => /usr/local/lib/lib3.so (0x00216000) But all of then are in the same folder as /usr/local/lib/{lib1,lib2