gnu-make

问题 I am looking to cross-compile an existing library which uses GNU autotools build system. I have a Linaro arm-gcc toolchain installed in my host machine and I am able to compile small programs directly using arm-gcc. Host machine: Ubuntu 12.04 Intel x64 Target machine: Ubuntu 14.04 ARM 32-bit (a board similar to Raspberry-Pi) I have a library source code which has configure.ac and Makefile.am files for it. I want to compile this code on host machine and generate ARM binaries which can be

问题 My directory contains 2 source files: a.c and b.c . I want to generate executable file a from a.c and b from b.c . Now I can only figure out one method to write Makefile: all: gcc -o a a.c gcc -o b b.c It seems a little awkward, is it better method? 回答1: The answers are fine, still I think you need some insight in how make works: The basic functionality of make is to create output files from input files if necessary . make decides what is necessary by comparing timestamps: If any input file

问题 I want to read the content of a text file and assign it to a variable in my makefile. I read the make manual ch 8.6: The file function , and wrote this simple snippet in my makefile: # Snippet from my makefile my_var = $(file < C:/full/path/to/my_file.txt) all: @echo $(my_var) I get the following error: *** Invalid file operation: < C:/full/path/to/my_file.txt. Stop. I deliberately choose for the $(file ..) instead of the $(shell ..) function to read out the file. That's because my makefile

问题 I have a tool which generates multiple output files, which is notoriously hard to model in make. I'm using the recipe at GNU Makefile rule generating a few targets from a single source file, which seems simple and reliable. And it almost works. Unfortunately, I'm seeing some very odd behaviour with regard to parallel builds, where it seems to be dropping dependencies sometimes; and I don't understand why. Here's my test case: out3: out1 out2 touch out3 .INTERMEDIATE: out.intermediate out1

问题 I am using the following simple Makefile to build some simple files. I am really new to making Makefile. I don't know why it keeps in rebuilding even though the files are built after first make and I am not editing any of the file. EXE = nextgenrsm CC = gcc LIBS = StarterWare_Files/ CFLAGS = -c INCLUDE_PATH = StarterWare_Files/ MAIN_SRC = $(wildcard *.c) MAIN_OBS = $(patsubst %.c,%.o,$(MAIN_SRC)) LIB_SRC = $(wildcard StarterWare_Files/*.c) LIB_OBS = $(patsubst StarterWare_Files/%.c,%.o,$(LIB

问题 I'm trying to 'make' using a pretty simple makefile. My makefile is named 'Makefile' so I'm simply using the command 'make'. I get this strange error: make: *** No rule to make target `/Makefile', needed by `Makefile'. Stop. If, however, I use make -f "full-path-to-makefile" it actually does run (with odd consequences...). I should say that I'm running all this from the directory where the Makefile lies, of course. I'm working on Mac OSX, using tcsh. Edit: I'm working in the LLVM framework,

问题 This is my current makefile. CXX = g++ CXXFLAGS = -Wall -O3 LDFLAGS = TARGET = testcpp SRCS = main.cpp object.cpp foo.cpp OBJS = $(SRCS:.cpp=.o) DEPS = $(SRCS:.cpp=.d) .PHONY: clean all all: $(TARGET) $(TARGET): $(OBJS) $(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJS) -o $(TARGET) .cpp.o: $(CXX) $(CXXFLAGS) -c $< -o $@ %.d: %.cpp $(CXX) -M $(CXXFLAGS) $< > $@ clean: rm -f $(OBJS) $(DEPS) $(TARGET) -include $(DEPS) It works perfectly with one exception. If the directory is already clean (no *.d, *.o) and

问题 I have a Makefile with a set of booleans which must be used to control the flags for an external application. The problem is that the flag must be passed as a comma-separated string. Something like this (non-working pseudo code): WITH_LIST = "" WITHOUT_LIST = "" ifeq ($(BOOL_A),y) # Append A to list "WITH_LIST" else # Append A to list "WITHOUT_LIST" endif ifeq ($(BOOL_B),y) # Append B to list "WITH_LIST" else # Append B to list "WITHOUT_LIST" endif ifeq ($(BOOL_C),y) # Append C to list "WITH

问题 I am trying to write a makefile which should pick the sources from src/ and headers from inc/ ~/Linuz/src: 1.c, 2.c, 3.c ... ~/Linuz/inc: abc.h, dyz.h Please help me to create a makefile which should be available at ~/Linuz/some_other_dir/Makefile PS: Trying to compile it for my linux machine. Thank you for your suggestions. 回答1: all: my_program %.o: ../src/%.c $(CC) $(CFLAGS) -I../inc/ -c -o $@ $^ my_program: 1.o 2.o 3.o $(CC) $(LDFLAGS) -o $@ $^ clean: rm -f *.o my_program If you put your

问题 I need debug old php version: PHP 5.6.22 (cli) (built: Jun 29 2016 14:26:09) Copyright (c) 1997-2016 The PHP Group Zend Engine v2.6.0, Copyright (c) 1998-2016 Zend Technologies On Ubuntu: Ubuntu 16.04 LTS I compiled appropriate PHP, and checked out xdebug from git repository: git://github.com/xdebug/xdebug.git I tried different versions, but just master seems compiling. In my errors I have: Failed loading /usr/share/php53/lib/php/extensions/no-debug-non-zts-20131226/xdebug.so: /usr/share