gnu-make

问题 In Racket's build system, we have a build step that invokes a program that can run several parallel tasks at once. Since this is invoked from make , it would be nice to respect the -j option that make was originally invoked with. However, as far as I can tell, there's no way to get the value of the -j option from inside the Makefile , or even as an environment variable in the programs that make invokes. Is there a way to get this value, or the command line that make was invoked with, or

问题 Lets say you filter for cpp files like so $(wildcard **/*.cpp) But you don't want files that contain the word foo and you don't want the file with the exact name bar.cpp How does one use filter-out with multiple criteria? 回答1: This seems to work. Also recursively. $(filter-out $(wildcard **/bar.cpp) $(wildcard **/*foo*), $(wildcard **/*.cpp)) Please also note Etan's simpler suggestion below. Leaving mine only for completeness. 来源： https://stackoverflow.com/questions/36719876/how-to-filter-out

问题 I wish to define a C macro by passing it as an argument to make , which is called from the command-line. Background: I want the directive #define ENABLE_OPT 1 to be included in my C source code when a certain build option is chosen. Thus, I want this to be done via the make command-line instead of modifying the source code or the makefile. How can this be achieved? I find that make -DENABLE_OPT=1 -f Makefile throws errors that 'E', 'N' etc. are invalid arguments to make. 回答1: You can use -

问题 Is there a way to tell automake not to interpret part of the Makefile.am? Specifically, I am trying to encode a Makefile conditional in a Makefile.am. As other people have noticed, this doesn't work because automake interprets the endif construct. Is there any way to escape or quote strings in Makefile.am files so that automake copies them verbatim into the destination Makefile? Specifically I don't want it to interpret the endif in something like: ifeq "$(SOMEVAR)" "" SOMEVAR="default_value"

问题 If I have the following rule in a makefile: $(OBJ)/%.o: $(SRC)/%.c $(CC) -c -o $@ $< $(CFLAGS) Every file matching the prefix ./obj/ and sufix .o will have its stem passed to % , so I can provide some dependencies based on its name. But, suppose I have this kind of rule, which I specify one by one the targets I want: OBJECTS=abc.o bca.o cba.o $(OBJECTS): $(SRC)/%.c $(CC) -c -o $@ $< $(CFLAGS) How do I make the % stem actually work for the current target name make is executing? Just using %

问题 I need a couple of symlinks in my project. From src/openlayers , folders img and theme have to be symlinked in contrib/openlayers . The contrib/openlayers folder should also be created automatically. .PHONY: run run: contrib/openlayers/theme contrib/openlayers/img ../bin/pserve development.ini --reload contrib/openlayers/theme: ln -s src/openlayers/theme $@ contrib/openlayers/img: ln -s src/openlayers/img $@ But this rule tries to create symlinks every time. (I put -f flag to ln , so it re

问题 I'm able to set PATH in a Makefile on Linux but not Mac OS X. With OS X, the PATH gets set but doesn't get used. Here's a demonstration: On CentOS 6 with bash 4.1.2(1)-release and GNU Make 3.81 $ pwd /tmp/experiment $ find * -type f -ls 132133 4 -rw-rw-r-- 1 tlim tlim 113 Aug 26 11:01 Makefile 132132 4 -rwxrwxr-x 1 tlim tlim 28 Aug 26 10:59 bin/myprog $ cat Makefile export PATH := $(shell /bin/pwd)/bin:$(PATH) what: @echo PATH=$$PATH @echo PATH=$(PATH) which myprog myprog $ cat bin/myprog #!

问题 I understand that this is a simple question but i am unable to find the reason/solution. I have defined a simple shell function in Makefile that is doing as follows, define my_function my_var="Hello"; echo $(my_var); echo Recvd arg = $(1); endef Please note that this is defined inside a makefile and I am using in one of my rule, $(obj_dir)/%.o: $(src_base)/%.cpp $(q)$(CXX) $(CXXFLAGS) -o $@ $(call my_function, $@) But the local variable my_var never gets assigned. I have tried many things

问题 I'm trying to create a Makefile that will download and process file a file to generate targets, this is a simplified version: default: all .PHONY: all clean filelist.d clean: @rm -fv *.date *.d #The actual list comes from a FTP file, but let's simplify things a bit filelist.d: @echo "Getting updated filelist..." @echo "LIST=$(shell date +\%M)1.date $(shell date +\%M)2.date" > $@ @echo 'all: $$(LIST)' >> $@ %.date: touch $@ -include filelist.d Unfortunately the target all doesn't get updated

问题 Assume 1000 files with extension .xhtml are in directory input, and that a certain subset of those files (with output paths in $(FILES), say) need to be transformed via xslt to files with the same name in directory output. A simple make rule would be: $(FILES): output/%.xhtml : input/%.xhtml saxon s:$< o:$@ foo.xslt This works, of course, doing the transform one file at a time. The problem is that I want to use saxon's batch processing to do all the files at one time, since, given the number