How can a macro definition be passed as an argument to make?

问题

I wish to define a C macro by passing it as an argument to make, which is called from the command-line.

Background: I want the directive #define ENABLE_OPT 1 to be included in my C source code when a certain build option is chosen. Thus, I want this to be done via the make command-line instead of modifying the source code or the makefile.

How can this be achieved? I find that make -DENABLE_OPT=1 -f Makefile throws errors that 'E', 'N' etc. are invalid arguments to make.

回答1:

You can use --eval, which will evaluate the string as a makefile statement:

make --eval="FLAGS+= -D ENABLE_OPT=1"

The make variable FLAGS is then used as a compiler argument to compile the code.

来源：https://stackoverflow.com/questions/39362327/how-can-a-macro-definition-be-passed-as-an-argument-to-make