gnu-make

问题 I'm new to the NDK. (using Windows). I have downloaded cygwin and the NDK. I have unzipped the NDK in C:\ . When I run cygwin I change to the NDK directory and I run the command build/host-setup.sh But I get: Error: could not find a valid GNU Make executable. I have downloaded GNU make 3.81 but still no luck. What do I have to do with GNU Make? Do I have to put it in a special directory or add it to PATH? 回答1: For anyone that comes across this, GNU make is not selected by default in the

问题 This may be simple but I've not been able to find the answer. I'm developing a gmake system for an embedded platform that has two processing elements, each with their own firmwares, call them CoreA.bin and CoreB, each with their own tree of dependencies. CoreB's make system is from a third party and has to be treated as a black box PHONY target. The bootloader updates them both from a single binary file, call it BinFile.bin which contains CoreA.bin and CoreB binaries rolled together. Thus the

问题 I was following Telegram's compile process at here and in the last step when compiling the app itself it gives me this error, to be brief the error's final lines are: CMakeFiles/MetaLang.dir/build.make:189: recipe for target 'MetaLang' failed make[2]: *** [MetaLang] Error 1 CMakeFiles/Makefile2:721: recipe for target 'CMakeFiles/MetaLang.dir/all' failed make[1]: *** [CMakeFiles/MetaLang.dir/all] Error 2 Makefile:83: recipe for target 'all' failed make: *** [all] Error 2 P.S. my OS is Ubuntu

问题 I have a makefile for compiling a static library. This makefile has a rule for compiling a unit test suite associated with the static library. Once the test suite is compiled, a python script is invoked to run the tests and log the results. It looks like this: unit: $(MAKE) -C cXbase/unit python $(TESTS_RUNNER) $(UNIT_TESTS_EXEC) $(UNIT_TESTS_LOG) I use Python to make the tests invocation portable. Right now, everything works fine: the tests compile and the test runner is called and logs

问题 Consider the following simple makefile: #------------------------------# # List all object files # #------------------------------# objects := main.o foo.o bar.o baz.o #------------------------------# # Define pattern rule # # for *.c -> *.o # #------------------------------# %.o: %.c $(CC) -c $(CFLAGS) $< -o $@ #------------------------------# # Define the rule to make # # the end result # #------------------------------# .PHONY all all: myApp.elf myApp.elf: $(objects) $(CC) $(objects) -o

问题 A big project usually has a complicated Makefile system. There are lots of variable definitions and target-prerequisity dependencies scattered in different Makefiles. Any handy way to print all the prerequisites and build rules for a target? To be specific, two questions: Question 1 say I have four Makefiles: Makefile1: p: a b [some rule] Makefile2: q: c d [some rule] Makefile3: r: e f [some rule] Makefile: all: p q r [some rule] Can I invoke some command to get some output similar to the

问题 I the GCC Wiki it is stated that support for auto-detection of dependencies has been available since version 4.6: Support the generation of Makefile dependencies via the -M... flags of GCC; you may need to specify additionally the -cpp option. The dependencies take modules, Fortran's include, and CPP's #include into account. Note: Using -M for the module path is no longer supported, use -J instead. In my program I have two Fortran files: module_1.f08 and main.f08 , where main uses module_1 .

问题 Specifically, I want to do something along the following lines. For a Makefile.am script that defines how a library file should be built, I want to be able to access a common library name throughout. For example, assuming I want the name of the library to be called 'name', I might start with the following variable: LIBNAME = name Then I might have something like this: lib_LTLIBRARIES = lib$(LIBNAME).la But then automake starts to complain when I want to do something like the following: lib$

问题 Suppose I have a Makefile: a.out: sleep 3 touch a.out a1 b.out: cat a1 > b.out c.out: a.out b.out cat a.out b.out > c.out make c.out will usually succeed, as the commands for a.out are executed before the commands for b.out. But make b.out will fail (in a clean directory), as will make -j c.out . As in real-life scenarios there is seldomly a sleep 3 and the bug will thus only show very randomly, I'm looking for a way to smoke out such errors with a higher probability. One idea would be to

问题 I have a makefile from which i am trying to invoke an executable, the executable needs 5 arguments, how do i pass these arguments from makefile doing this does not works run-exe: arg1 = "somevalue" arg2 = "somevalue" arg3 = "somevalue" arg4 = "somevalue" arg5 = "somevalue" $(ExeFolderPath)/Task $(arg1) $(arg2) $(arg3) $(arg4) $(arg5) the arguments are getting ignored. 回答1: Each line in the recipe of the run-exe rule runs in a different shell instance. So, if you set a variable in one line,