gnu-make

问题 How to use multiple-line variable in recipe? file-name: multiple-line-variable define foo = echo welcome endef export foo all: echo $(foo) I get following output. But i expect 'welcome' print. $ make -f multiple-line-variable echo 回答1: SunEric's answer didn't correctly explain what was happening. Adding, or not, the @ has absolutely zero to do with the reason you're not seeing "welcome" printed. The reason your original example did not work as expected is because you're reading the GNU make

问题 I have to port a project from IBM AIX to Linux. It is using make that comes IBM AIX on AIX. My question is whether the syntax of IBM AIX make utility compatible with syntax of gnu make ? I mean can I use same makefiles with gnu make too without any changes? Thanks 回答1: No, they're incompatible in general. However, if the IBM AIX Makefile uses only features mandated by POSIX make, there might be a chance to get it working unmodified on Linux with GNU make . It is impossible to tell without

问题 I had a simple variable definition in my makefile: THIS := ~/edan and it had trailing spaces in the line. Later, when I defined another variable in terms of this one: WARES := $(THIS)/wares the actual variable defined was /home/directory/edan wares and then the make clean rule removed /home/directory/edan instead of what I wanted it to. How can I prevent a makefile from executing if a line has trailing spaces? 回答1: Although you could write the Makefile so that it checks the variable for

问题 I am trying to build a Makefile that can build both release and debug targets by specifying a target rather than a variable (such as make debug=1 , not great) I have a condensed simplified example here that emulates what I am trying to achieve: ifdef debug BINARY=my_binary_debug MODULE_1_BIN=abc_debug MODULE_2_BIN=xyz_debug export DBG=1 else BINARY=my_binary MODULE_1_BIN=abc MODULE_2_BIN=xyz endif FLAG=something .PHONY: all debug clean all: bin/$(BINARY).bin bin/$(BINARY).bin: module_1/$

问题 I have the following rule: SPECIAL = file1 file2 %.o : %.cpp a.h $(CC) -c $(CFLAGS) $< -o $@ I would like that if % is in $(SPECIAL) , then b.h is added to the list of dependencies. Is there a way to do it, without repeating the rule? 回答1: You can assign additional dependencies separately. Just add a line at the end: $(addsuffix .o,${SPECIAL}): b.h To not have to deal with dependency order, replace $< in the rule with $(filter %.cpp,$^) . This way %.cpp does not have to be the first

问题 So in my project I have a src directory and an obj directory. I'm recursively finding the .c and .cpp files in my src directory, and then its corresponding .o file gets put right in the obj directory. So for example if I have a .cpp file: src/dir1/dir2/file.cpp , its corresponding .o file would be obj/file.o . Then I'm generating the rule to get the .o file from the .cpp file using a make foreach function using this code: rwildcard=$(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2)$(filter

问题 I have the following files in a directory: FP01.c: #include <stdio.h> #include <stdlib.h> int main(void) { long double ld = 0.1L; // long double constant (L or l suffix) scanf("%Lf", &ld); return 0; } makefile: MAKEFLAGS += -rR # the default target .PHONY: all all: FP01.elf %.elf: % cp $< $@ # prevents non-terminal match-anything rules from matching target '%.c' # see section 10.5.5 of GNU make manual %.c: # a non-terminal match-anything rule %: %.c gcc -Wall -g $< -o $@ If FP01 does not

问题 The Makefile below has to create (multiple) output directories, and generate output in those directories, from input in the directory above. So, on entry, dir n exists, and dir n /file.foo exists. The build has to create dir n /out/file.bar. This Makefile works when run as a single job (note that it creates the two required source directories and files in the $(shell) ). It presumably works because makedirs is the first/leftmost prerequisite for all . However, it doesn't work for a multi-job

问题 So I have the exact same question as the one below, but no one has answered it. Pattern matching Makefile with multiple executable targets I am trying to build a series of small test files each have a pattern of "test*.c" to test my library. I wanted to write a makefile that builds executables for every one of the test files all at once (each name: test1, test2, test3..etc.). However, I am not sure how to achieve that. What I have so far is the following: SRC := $(shell find *.c) ALL_PROG :=

问题 So I have the exact same question as the one below, but no one has answered it. Pattern matching Makefile with multiple executable targets I am trying to build a series of small test files each have a pattern of "test*.c" to test my library. I wanted to write a makefile that builds executables for every one of the test files all at once (each name: test1, test2, test3..etc.). However, I am not sure how to achieve that. What I have so far is the following: SRC := $(shell find *.c) ALL_PROG :=