gnu-make

问题 I have a phony debug and asm target. debug works by updating the variable CFLAGS and then compiles the normal target, which uses these new CFLAGS to produce debug symbols. This works as intended. Analogously I want to define the asm target set the -S switch and to change the output name from file to file.s . However, the last part does not work, and I get: $ make asm -B gcc -fmessage-length=0 -ansi -pedantic -Werror -Wall -Wextra -Wwrite-strings -Winit-self -Wcast-align -Wcast-qual -Wpointer

问题 BACKGROUND This is related to my question GNU make - transform every prerequisite into target (implicitly) I've posted this question because it's interesting and may be useful by itself - to understand make - and I don't want it to get lost in the "original" question. INFO I have a file Dummy.mk : %:: null @: null: @: which I pass to my make as make all MAKEFILES=Dummy.mk . When I replace null with saflkjsaflkjdsa , %:: saflkjsaflkjdsa @: saflkjsaflkjdsa: @: the behavior of the build was

问题 I started a simple makefile for my project (MS-windows target, MinGW) with the following : CFLAGS = -g -O0 -Wall -std=c99 CC = gcc CPP = g++ LIBS = PBDUMPER = pbdumper.exe all: $(PBDUMPER) $(PBDUMPER): pbdumper.c $(CC) $(CFLAGS) -o $@ $< $(LIBS) clean: rm -f $(PBDUMPER) .PHONY: clean Now I would like to choose between release and debug compilation. I have changed the variable definitions and implicit rule for debug : CFLAGS_COMMON = -std=c99 CFLAGS_DEBUG = -g -O0 -Wall CFLAGS_RELEASE = -O2

问题 In my Makefile, I want to check if a certain file exists, do something, and check again. Using gnu make, I cannot. Here is the simple example: $(info $(wildcard OK)) $(shell touch OK) $(info $(wildcard OK)) If I run make once, I see two empty lines. If I run make again, both lines are OK . I thought, maybe $(eval) will let me get the updated answer. Alas, $(eval $$(info $$(wildcard OK))) produces the same answer, as if make has some way to predict all wildcard calculations before it starts

问题 I have a data conversion process that is driven by GNU make. It takes human-generated input files and creates output files using a conversion progam. Obviously this is about as simple as a makefile can get: inputs=$(wildcard *.input) outputs=$(subst .input,.output, $(inputs)) .PHONY: all all: $(outputs) %.output: %.input converter $< -o $@ It gets even easier; converter knows the location of the output file from the input file, so we don't need $@ : %.output: %.input converter $< So far, so

问题 So I want to comment variable definitions in Makefile in-line. The problem is that Make doesn't strip white spaces between the definition and its comment. Here is an example of what I mean: OPTS += -DBLA # Does bla OPTS += -DBLUBB # Does blubb OPTS += -DEND .PHONY test test: @echo $(OPTS) The output of this is -DBLA -DBLUBB -DEND with annoying extra white spaces between the options. What I want is this: -DBLA -DBLUBB -DEND How do I get around this Problem? The Make string function @echo $

问题 I have a C project with the following Makefile : CC=mpicc buildsDir: ./builds mkdir ./builds main: ./builds message dh main.c $(CC) -o ./builds/main main.c ./builds/dh.o ./builds/message.o -g -lcrypto -lssl dh: ./builds dh.c dh.h $(CC) -c -o ./builds/dh.o dh.c -g -lcrypto -lssl message: message.c message.h $(CC) -c -o ./builds/message.o -g ./message.c run: main mpirun -quiet -np 3 xterm -hold -e ./builds/main & debug: main mpirun -quiet -np 3 xterm -e gdb ./builds/main .PHONY: clean clean: rm

问题 I have a number of files from this expression: ui_files := $(wildcard $(SUBDIRS:%=%/*.ui)). Now I need the list of the same file paths, but with "ui_" prefix in file name and another extension (.h). How can I do that? 回答1: You can iterate over the list using foreach and transform each element: h_files := $(foreach ui,$(ui_files),$(dir $(ui))ui_$(notdir $(ui:.ui=.h))) Or, first transform the whole list and then use join: h_files := $(join $(dir $(ui_files)),$(patsubst %.ui,ui_%.h,$(notdir $(ui

问题 I'm still trying to build VTK on windows. I have installed Cygwin and I'm done configuring with CMake I think. However I'm facing the error that you can see on the screenshot below: the make command somehow tries to make through MS Visual Studio while I want to use the GNU make. I'm guessing this comes from either the makefile itself which could force that behaviour or from my Cygwin settings. Thanks in advance for the help Makefile content: # CMAKE generated file: DO NOT EDIT! # Generated by

问题 I am trying to use a nested for loop for searching and copying some files inside the recipe of one of the targets inside a makefile: DIR = $(DIR_A) $(DIR_B) install: for dirs in $(DIR); do \ for file in $(shell find $(dirs) -type f -and -not -path "*/.svn*" | sed -e "s|$(dirs)||"); do \ folder=$${file%/*}; \ $(INSTALL) -d $(DEST_DIR)$$folder/log; \ $(INSTALL) $(dirs)/$$file $(DEST_DIR)$$folder/log; \ done \ done However $(dirs) variable always evaluates to empty inside the second for loop and