gnu-make

问题 I need to build targets with names like, v1/thread4/foo v1/thread8/foo v1/thread16/foo v2/thread4/foo v2/thread8/foo v2/thread16/foo I want to match the thread% and v% , because for my code, the threadNum=? and the Version=? are the Macros need to define in the compile time. so in the result, I hope to get a layout like, and the foo is the executable name v1-|thead4/foo |thead8/foo |thead16/foo v2-|thead4/foo |thead8/foo |thead16/foo I've tried ways like, it doesn't work %/%/foo: foo.cc $

问题 I want to tell make that it shall always use -j4 option even if I didn't specify it vie command line. Normally i would do this in some configuration file (i.e. ~/.makerc ). Does such file exist for gnu make? 回答1: Have a read about the $(MAKEFLAGS) variable: export MAKEFLAGS=j4 However this will likely interfere with recursive-make-based builds (not that sensible people are using recursive make anyway!), by interfering with GNU make's ability to communicate with its sub-makes. So the more

问题 I want to tell make that it shall always use -j4 option even if I didn't specify it vie command line. Normally i would do this in some configuration file (i.e. ~/.makerc ). Does such file exist for gnu make? 回答1: Have a read about the $(MAKEFLAGS) variable: export MAKEFLAGS=j4 However this will likely interfere with recursive-make-based builds (not that sensible people are using recursive make anyway!), by interfering with GNU make's ability to communicate with its sub-makes. So the more

问题 From the documentation for GNU make: http://www.gnu.org/software/make/manual/make.html#Parallel When the system is heavily loaded, you will probably want to run fewer jobs than when it is lightly loaded. You can use the ‘-l’ option to tell make to limit the number of jobs to run at once, based on the load average. The ‘-l’ or ‘--max-load’ option is followed by a floating-point number. For example, -l 2.5 will not let make start more than one job if the load average is above 2.5. The ‘-l’

问题 I have a problem with order-only prerequisites. These do not execute first at all. Am I mis-understanding the way order-only prerequisites work? The following make script: .PHONY: mefirst mefirst2 mefirst: @echo "I'm first!" mefirst2: @echo "I'm first too!" normaltarget: normaltarget2 | mefirst2 @echo "normaltarget done" normaltarget2: a b c @echo "normaltarget2 done" helloworld: normaltarget | mefirst @echo "helloworld done" .DEFAULT_GOAL := go go: helloworld @echo "go done" a: @echo a b:

问题 I came across several SO questions regarding specific aspects of improving the turn-around time of CMake enabled C++ projects lately (like "At what level should I distribute my build process?" or "cmake rebuild_cache for just a subdirectory?"), I was wondering if there is a more general guidance utilizing the specific possibilities CMake offers. If there is probably no cross-platform compile time optimization, I'm mainly interested in Visual Studio or GNU toochain based approaches. And I'm

问题 I'm working on a makefile environment for an FPGA team and I'm currently having issues with a macro. I have it defined as shown for the TOOL_EXEC variable, but I'm getting an "unexpected token" error related to the double quotes and parenthesis. If I put double double quotes the variable inflates without any quotations at all and yields no error, however our tool requires them to be in parenthesis. I need to pass the fully quoted parenthesis information, but the macro definition is giving me

问题 I wrote a cowboy project that I start on localhost with gmake run . When I make run on a fresh installation, this error happens: ~/tunnel# make run erlang.mk:24: Please upgrade to GNU Make 4 or later: https://erlang.mk/guide/installation.html make[1]: Entering directory `/root/tunnel/deps/cowboy' ../../erlang.mk:24: Please upgrade to GNU Make 4 or later: https://erlang.mk/guide/installation.html make[2]: Entering directory `/root/tunnel/deps/cowlib' ../../erlang.mk:24: Please upgrade to GNU

问题 In (GNU) make, I want a variable to be assigned a value when the build chain of specific targets are starting. For targets a.so and b.so , each depending on b.o , I can do this manually like this: # Rules all: a.so b.so a.so: b.o @echo Current .so is $(current) touch $@ b.so: b.o @echo Current .so is $(current) touch $@ b.o: @echo Current .so is $(current) touch $@ # Set the "current" variable based on which .so is being build a.so: current = a.so b.so: current = b.so Here, current has the

问题 I have the following directory structure. Project/ ├── bin/ ├── src/ │ ├── main.c │ ├── util/ │ ├── util.c │ ├── util.h ├── obj/ ├── .depend/ All my source code are in the src folder. In the src root is my main.c file; which includes other files that are on the same level that he (or within a same level folder). I have a Makefile below that works well for all files in the same level of main.c but does not work on files in a subfolder within src How change my Makefile to allow subfolder within