gnu-make

Overriding `CC` and `CXX` variables in makefiles

邮差的信 提交于 2020-01-02 09:44:34
问题 I have a master makefile, which contains generic settings, and a child makefile that has project specific settings. From my other question about overriding variables in a makefile, I learned that I can use the following code in my master makefile: CC ?= avr-gcc CXX ?= avr-g++ In the child makefile, I use colorgcc and override these variables: CC ?= color-avr-gcc CXX ?= color-avr-g++ Everything works. But, if I remove the above lines from my child makefile, make starts using gcc and g++

How can I force Make to execute a recipe all the time

人走茶凉 提交于 2020-01-02 05:41:06
问题 The current Makefile has something like this: target1 : lib1.a lib2.a target2 : lib1.a lib3.a target3 : lib3.a lib1.a: $(MAKE) -C sub_dir all I want to change this Makefile so that wherever a target depends on lib1.a , it always run the command " $(MAKE) -C sub_dir all ", always. Another words, in the above example, target1 and target2 will always run " $(MAKE) -C sub_dir all ". Is there any way I can do that? I know the following does not work: target1 : lib2.a $(MAKE) -C sub_dir all target2

Out of tree builds with makefiles and static pattern rules

大城市里の小女人 提交于 2020-01-02 01:20:11
问题 I'm working on some bare-metal embedded code that runs on ARM, and thus has to deal with the whole ARM vs. THUMB mode distinction. The current build system uses static pattern rules to determine whether to compile files in ARM or THUMB mode. $(ACOBJS) : %.o : %.c @echo $(CC) -c $(CFLAGS) $(AOPT) -I . $(IINCDIR) $< -o $@ $(TCOBJS) : %.o : %.c @echo $(CC) -c $(CFLAGS) $(TOPT) -I . $(IINCDIR) $< -o $@ Where ACOBJS is a list of output objects that should be in ARM mode and the same for TCOBJS and

Makefile generic pattern rule — xyzzy-en_US.ext2 from xyzzy.ext0

别等时光非礼了梦想. 提交于 2020-01-01 06:54:24
问题 I can't figure out a way to define a generic pattern rule for the following kind of production with make: require xyzzy-en_US.ext2 from xyzzy.ext0 via xyzzy.ext1 . This works: all: xyzzy-en_US.ext2 # to be compiled from xyzzy.ext0 %.ext1 : %.ext0 # produce xyzzy.ext1 %-en_US.ext2 : %.ext1 # produce xyzzy-en_US.ext2 But how to generalize the locale part of the second rule? Or do I need to generate rules for all different locales? Neither of these work: %-??_??.ext2 : %.ext1 # ... %.ext2 : $(@,

GCC build time doesn't benefit much from precompiled headers

风流意气都作罢 提交于 2020-01-01 01:54:11
问题 I have a huge project, something about 150 000 LOC of C++ code. Build time is something about 15 minutes. This project consists of many sub-projects of different sizes. I have built separate precompiled headers for each subproject, but when I use them build time stays roughly the same. It seemed that build time is 5-10% percent less, not more. Precompiled headers is definitely used, I use -Winvalid-pch option and I have tried to compile with -H compiler option, my precompiled headers appears

Generate multiple target using single action/rule

白昼怎懂夜的黑 提交于 2020-01-01 01:52:13
问题 How do I write a rule to generate set of files using a single action. Example: Files x , y , z are generated as a result of single execution of script t.sh which takes file a as input. x y z: a t.sh $@ GNU make tries to execute t.sh 3 times. 回答1: You could implement one of the solutions specified in the automake manual. Because you've tagged this gnumake , I should also point out that using a GNU make pattern rule (the ones with % ) with multiple targets WILL consider both generated from one

How can I capture the current directory as an absolute pathname in a make variable?

自古美人都是妖i 提交于 2020-01-01 01:10:28
问题 I'd like to get the current directory during a GNUmake file run put into a make variable. What is the syntax to do this? Something like this? DIR := $(PWD) 回答1: Um, no, $PWD is sometimes defined in your environment and thus inherited by make, but oftentimes not. You need $CURDIR . DIR := ${CURDIR} 来源: https://stackoverflow.com/questions/3050231/how-can-i-capture-the-current-directory-as-an-absolute-pathname-in-a-make-variab

telling 'make' to ignore dependencies when the top target has been created

纵饮孤独 提交于 2019-12-31 17:56:45
问题 I'm running the following kind of pipeline: digestA: hugefileB hugefileC cat $^ > $@ rm $^ hugefileB: touch $@ hugefileC: touch $@ The targets hugefileB and hugefileC are very big and take a long time to compute (and need the power of Make). But once digestA has been created, there is no need to keep its dependencies: it deletes those dependencies to free up disk space. Now, if I invoke 'make' again, hugefileB and hugefileC will be rebuilt, whereas digestA is already ok. Is there any way to

How can I highlight the warning and error lines in the make output?

耗尽温柔 提交于 2019-12-31 08:08:34
问题 Sometimes, make's output fills the screen. It's a little bit hard to identify all the warning and error message lines. I know may shell color output can help Can anyone can help me? 回答1: Have a look at colormake , found here $ apt-cache search colormake colormake - simple wrapper around make to colorize output Using the power of google, I also found this bash-function. make() { pathpat="(/[^/]*)+:[0-9]+" ccred=$(echo -e "\033[0;31m") ccyellow=$(echo -e "\033[0;33m") ccend=$(echo -e "\033[0m")

Global default settings for cmake

一个人想着一个人 提交于 2019-12-31 06:58:07
问题 Is there anything similar to MAKEFLAGS environment variable for cmake , to set some global defaults like CMAKE_INSTALL_PREFIX ? 回答1: No, there is no similar environment variable for CMake. Everything you can set through environment variables in CMake is documented here. But you could use a the "preload cache" -C option and put all reoccurring settings in an appropriate script (see e.g. CMake preload script for cache). 来源: https://stackoverflow.com/questions/47452508/global-default-settings