gnu-make

问题 I have a makefile snippet: all: $(objects) fresh: all | clean directory directory: ;mkdir -p OutputDirectory clean: ;rm $(objects); rm -rf OutputDirectory Here, I want to ensure that when I do make fresh - clean should succeed by directory which should be followed by all . Semantically, here it might not make sense for clean to be order only prerequisite. Assume it to some order only dependency that has to be executed in some order. The following link shows similar problem but for normal

问题 I have a c project with directory layout like this src1 -a.c -b.c src2 -c.c -d.c objects I'm trying to compile a/b/c/d into objects files and saved them into objects directory and here is part of my Makefile. src1 = src1/ src1 = src2/ obj = objects/ src1_files = a.c b.c src2_files = c.c d.c source_files = $(addprefix $(src1), $(src1_files)) $(addprefix $(src1), $(src2_files)) objects := $(addprefix $(obj), $(src1_files:.c=.o)) $(addprefix $(obj), $(src2_files:.c=.o)) $(obj)%.o: $(source_files

问题 In gnu make, is there a way to get hold of the original target that initiated the whole chain and lead the execution to the current recipe? .PHONY : all clean common all: common clean: common common: @echo $@ @echo $(MAKECMDGOALS) @for a in $$(ls); do \ if [ -d $$a ]; then \ echo -C $$a $(MAKECMDGOALS); \ #$(MAKE) -C $$a $(MAKECMDGOALS); \ fi; \ done; @echo "Done!" As in the above example, when I run the 'make all' or 'make clean', I can use $(MAKECMDGOALS) to tell which target was passed to

问题 In gnu make, is there a way to get hold of the original target that initiated the whole chain and lead the execution to the current recipe? .PHONY : all clean common all: common clean: common common: @echo $@ @echo $(MAKECMDGOALS) @for a in $$(ls); do \ if [ -d $$a ]; then \ echo -C $$a $(MAKECMDGOALS); \ #$(MAKE) -C $$a $(MAKECMDGOALS); \ fi; \ done; @echo "Done!" As in the above example, when I run the 'make all' or 'make clean', I can use $(MAKECMDGOALS) to tell which target was passed to

问题 We use GNU Make for our system. At the end of our makefiles, we have an include called Makedepends which generates a bunch of .d files using -MM switch on gcc. We then include the .d file for each .cc file using an include $(CXXFILES:.cc=.d) line. But when we delete file or move files, the dependancies step breaks and we have to manually delete the .d files (even a make clean doesn't work because the dependencies fail) Is there a way to generate these dependency .d files or include these

问题 Does anyone know how to use a here-document redirection on a recipe? test: sh <<EOF echo I Need This echo To Work ls EOF I can't find any solution trying the usual backslash method (which basically ends with a command in a single line). Rationale: I have a set of multi-line recipes that I want to proxy through another command (e.g., sh, docker). onelinerecipe := echo l1 define twolinerecipe := echo l1 echo l2 endef define threelinerecipe := echo l1 echo l2 echo l3 endef # sh as proxy command

问题 I usually use a high level build system like cmake for building my C/C++ code. But for various reasons I am using straight GNU make . I am doing recursive build where each directory has a makefile. I recently had to change all my makefiles from using make to $(MAKE) and then parallel builds started working. The literature I've read all say "always use $(MAKE) " (O'Reilly book, 5+ solutions on stackoverflow.com from people with greater than 10-40K points). In your makefiles, why always use $

问题 I am new in make file. I have a program made of main.cpp types.hpp application/coordinator.hpp application/correlation.hpp application/handler.hpp application/settings.hpp libraries/basket.hpp libraries/config.hpp libraries/graphics.hpp ... I have so many files and the list of my files will be updated so many times. I want the make file recognizes automatically which .o file to be generated or updated. I don't want to update my make file each time I create and include a new file. The output

问题 I am using MinGW under Windows 10 for my development tools. I have a C project with ~100 source files. I created a makefile to build the project, and it worked fine, every time. But then I tried to speed up the build by passing -j4 to mingw32-make , telling it to use four processors in parallel. This did indeed speed up the build, but only for a while: after a seemingly random number of compilations (the number changes every time), I get the error gcc.exe: error: CreateProcess: No such file

问题 I am using MinGW under Windows 10 for my development tools. I have a C project with ~100 source files. I created a makefile to build the project, and it worked fine, every time. But then I tried to speed up the build by passing -j4 to mingw32-make , telling it to use four processors in parallel. This did indeed speed up the build, but only for a while: after a seemingly random number of compilations (the number changes every time), I get the error gcc.exe: error: CreateProcess: No such file