gnu-make

.SECONDARY for a pattern rule with GNU Make

强颜欢笑 提交于 2020-01-10 02:35:06
问题 I want to use the special target .SECONDARY of GNU Make to specify that the results of a particular pattern rule should not be deleted when created as a intermediate files. .PRECIOUS works with patterns, but oddly enough, not .SECONDARY. I don't want to use .PRECIOUS, because I do want the file to be deleted in the case that Make is interrupted by a signal, or the command returns a non-zero exit status when used in combination with .DELETE_ON_ERROR. Any suggestions? 回答1: You can use

Pattern only matches once per invocation and make is deleting intermediate files

余生长醉 提交于 2020-01-07 05:23:10
问题 I have the following rules in a Makefile to build an executable in 3 stages: all: build/myexe build/myexe: output/main_dats.o output/foo_dats.o | build/ gcc $^ -o $@ output/%.o: output/%.c patscc -c $< -o $@ output/%_dats.c: src/%.dats | output/ patsopt -cc -o $@ -d $< build/: mkdir -p build/ output/: mkdir -p output/ An src/%.dats source file is used to generate an output/%_dats.c source file which is compiled to an output/%.o object file and finally they are linked into the executable build

How to use synchronization in makefile?

蹲街弑〆低调 提交于 2020-01-07 03:25:08
问题 From the docs: To avoid this you can use the --output-sync ( -O ) option. This option instructs make to save the output from the commands it invokes and print it all once the commands are completed. Additionally, if there are multiple recursive make invocations running in parallel, they will communicate so that only one of them is generating output at a time. So, given a makefile: # A "recipe" that will always fail. all:: @foo bar baz And running, we get: # A "non-synchronized" run $ make

Can I use GNU make's SHELL variable to connect to a remote shell?

孤街浪徒 提交于 2020-01-06 19:57:42
问题 One of the projects I'm working on uses gnu make for testing. I would like to test on a platform that doesn't have a make implementation, but does have a POSIX shell. Is it possible to create a script (preferably in python) that can "stitch" a remote shell to make, and put it in make's SHELL environment variable? If not, is there another way anyone can think of to do it? 回答1: It is possible. Create a script that forwards commands to a remote host. For example: #!/bin/bash shift # remove -c

can't figure out Makefile with complicated dependencies

被刻印的时光 ゝ 提交于 2020-01-06 18:08:21
问题 I have a task at hand where my source file is under: apps/$(APP_NAME)/$(APP_ENV)/$(APP_NAME).yml then I need to process those files into: .output/$(APP_NAME)/$(APP_ENV).yml I am failing to sort out the rules for such Makefile where my APP_NAME is dynamic and comes from APP_NAMES=$(shell ls -1 $(APP_DIRS)) I am able to do singular dependencies no problem: OUTPUT_DIR:=.output APPS_DIR:=apps $(OUTPUT_DIR)/app1/prod.yml: $(APPS_DIR)/app1/prod/app1.yml $(eval APP_ENV=$(patsubst %.yml, %, $

can't figure out Makefile with complicated dependencies

﹥>﹥吖頭↗ 提交于 2020-01-06 18:07:27
问题 I have a task at hand where my source file is under: apps/$(APP_NAME)/$(APP_ENV)/$(APP_NAME).yml then I need to process those files into: .output/$(APP_NAME)/$(APP_ENV).yml I am failing to sort out the rules for such Makefile where my APP_NAME is dynamic and comes from APP_NAMES=$(shell ls -1 $(APP_DIRS)) I am able to do singular dependencies no problem: OUTPUT_DIR:=.output APPS_DIR:=apps $(OUTPUT_DIR)/app1/prod.yml: $(APPS_DIR)/app1/prod/app1.yml $(eval APP_ENV=$(patsubst %.yml, %, $

Inconsistent expansion by make for the '$?' variable

房东的猫 提交于 2020-01-06 07:32:48
问题 From the docs: $? The names of all the prerequisites that are newer than the target, with spaces between them. So, given a makefile: # Force make to search for 'foo' in the VPATH directory $(shell rm -rf foo) # If 'D' is a "regular" file, we remove it first. $(shell rm -rf D) $(shell mkdir D) # Suggest a VPATH-file, for Make to "associate" with 'foo'. $(shell touch D/foo) $(shell sleep 1) # Target 'all' is newer than prerequisite 'D/foo' $(shell touch all) VPATH = D all : foo phony echo '$?'

How to exclude a particular file with GNUMake's wildcard function?

淺唱寂寞╮ 提交于 2020-01-06 05:25:16
问题 My project's directory structure is as follows: My Makefile looks like this: dir1_contents := $(wildcard dir1/*) dir3_contents := $(wildcard dir3/*) all: clean_dir1 clean_dir3 clean_dir1: echo 'dir1_contents = $(dir1_contents)' clean_dir3: echo 'dir3_contents = $(dir3_contents)' When I run make, this is what I get: $ pwd make-test $ make -s dir1_contents = dir1/dir2 dir1/file2.junk dir1/file3.junk dir3_contents = dir3/file4.junk I want to get the contents of dir1 in dir1_contents . But I want

How to strip out a -D for just one file in a gnu makefile?

懵懂的女人 提交于 2020-01-05 07:13:54
问题 I have '-Wredundant-decls' in my CXXFLAGS but for one file, I want it removed. In my GNU makefile, how can I structure a rule to remove just that part of the CXXFLAGS. I know how to add only for that file, I would do something like this: $O/just_one_file.o: CXXFLAGS += -Wredundant-decls So, ideally I'd do something like this (which doesn't work) to remove it: $O/just_one_file.o: CXXFLAGS -= -Wredundant-decls However, maybe with some $ magic, I can construct some kind of sed or perl script to

How to strip out a -D for just one file in a gnu makefile?

佐手、 提交于 2020-01-05 07:12:42
问题 I have '-Wredundant-decls' in my CXXFLAGS but for one file, I want it removed. In my GNU makefile, how can I structure a rule to remove just that part of the CXXFLAGS. I know how to add only for that file, I would do something like this: $O/just_one_file.o: CXXFLAGS += -Wredundant-decls So, ideally I'd do something like this (which doesn't work) to remove it: $O/just_one_file.o: CXXFLAGS -= -Wredundant-decls However, maybe with some $ magic, I can construct some kind of sed or perl script to