gnu-make

make error 2 on Windows when building fastText

爱⌒轻易说出口 提交于 2020-01-14 06:16:14
问题 I'm trying to build fastText (Facebook's library for learning of word representations and sentence classification) and have tried followed the instructions on their Github page: $ git clone git@github.com:facebookresearch/fastText.git $ cd fastText $ make I installed GnuWin32 and added to the path in order to use the make function. I'm on Windows 10. However I get the following error: $ make c++ -pthread -O3 -funroll-loops -std=c++0x -c src/args.cc process_begin: CreateProcess(NULL, c++

the behavior when a gnu make phony target happens to be the same as a directory name

不问归期 提交于 2020-01-14 05:31:05
问题 A makefile has a phony target libs , and also a directory libs to descend into. On one machine it works well, and another it does not descend into libs directory for the libs target. In both cases the gnu make version is 3.81, but one on windows and another on a centos. The top make file: $ cat Makefile SUBDIRS := libs .phony: all headers libs exes all: headers libs exes headers libs exes: @for d in $(SUBDIRS); do \ echo -e "\n\n"; \ echo -e "=================\n"; \ echo -e " ++Build subdir $

GNU Make recursively expanded variables examples

瘦欲@ 提交于 2020-01-14 03:40:29
问题 Could somebody provide a real-world example of using recursively expanded variables (REV)? In the docs or various blog posts people give only useless toy examples, like foo = $(bar) bar = $(ugh) ugh = Huh? I cannot find a real use for REV besides creating custom functions with $(call) . I also found that in the past people were using REV to supply additional parameters to a compiler for specific targets but that trick is considered outdated now because GNU Make has target-specific variables.

Qt and MOC woes with a simple make

那年仲夏 提交于 2020-01-13 19:06:24
问题 I guess this is more of a GNU Make question than Qt and moc, but here goes. I have a directory which contains multiple Q_OBJECTS , and I have some simple code, which collects all these, e.g MOCS := $(shell grep -l Q_OBJECT $(HEADERS)) Assume HEADERS is a collection of the header files in the "current location" Now what I would like to do is specify a rule which will call Qt moc to build the .C file and then compile that into an object. How would one specify such a rule? My starting point is

Qt and MOC woes with a simple make

拥有回忆 提交于 2020-01-13 19:06:09
问题 I guess this is more of a GNU Make question than Qt and moc, but here goes. I have a directory which contains multiple Q_OBJECTS , and I have some simple code, which collects all these, e.g MOCS := $(shell grep -l Q_OBJECT $(HEADERS)) Assume HEADERS is a collection of the header files in the "current location" Now what I would like to do is specify a rule which will call Qt moc to build the .C file and then compile that into an object. How would one specify such a rule? My starting point is

Makefile: all vs default targets

不打扰是莪最后的温柔 提交于 2020-01-13 08:12:06
问题 Talking with respect to GNU make, what is the difference between PHONY targets all: and default: . CC=g++ default: hello hello: hello.cpp $(CC) -o hello hello.cpp and CC=g++ all: hello hello: hello.cpp $(CC) -o hello hello.cpp Both of them do the same job. 回答1: You can call them shirley if you like; neither of the labels you mention has any special semantics. The default behavior of make is to run the first target in the Makefile if you don't specify a target as a command-line argument. If

Cannot call bash function inside makefile

拥有回忆 提交于 2020-01-12 05:28:11
问题 I have an impression that I can call bash function inside GNU makefile, but seems wrong. Here is a simple test, I have this function defined: >type lsc lsc is a function lsc () { ls --color=auto --color=tty } Here is my Makefile: >cat Makefile all: lsc Here is what I get in running make: >make lsc make: lsc: Command not found make: *** [all] Error 127 Is my impression wrong? Or is there any env setup issue? I can run "lsc" at the command line. 回答1: You cannot call bash functions or aliases in

How to recompile just a single kernel module?

99封情书 提交于 2020-01-11 15:05:39
问题 Usually kernel source are stored in /usr/src/linux-2.6.x/ . To avoid to recompile the entire kernel if I modify a module's source, how can I recompile just that module? 回答1: Switch to the root directory of your source tree and run the following command: $ make modules SUBDIRS=drivers/the_module_directory And to install the compiled module: $ make modules_install SUBDIRS=drivers/the_module_directory Note: As lunakid mentions, the latter command might not build the module first, so be careful.

How to recompile just a single kernel module?

十年热恋 提交于 2020-01-11 15:04:30
问题 Usually kernel source are stored in /usr/src/linux-2.6.x/ . To avoid to recompile the entire kernel if I modify a module's source, how can I recompile just that module? 回答1: Switch to the root directory of your source tree and run the following command: $ make modules SUBDIRS=drivers/the_module_directory And to install the compiled module: $ make modules_install SUBDIRS=drivers/the_module_directory Note: As lunakid mentions, the latter command might not build the module first, so be careful.

How to recompile just a single kernel module?

女生的网名这么多〃 提交于 2020-01-11 15:04:21
问题 Usually kernel source are stored in /usr/src/linux-2.6.x/ . To avoid to recompile the entire kernel if I modify a module's source, how can I recompile just that module? 回答1: Switch to the root directory of your source tree and run the following command: $ make modules SUBDIRS=drivers/the_module_directory And to install the compiled module: $ make modules_install SUBDIRS=drivers/the_module_directory Note: As lunakid mentions, the latter command might not build the module first, so be careful.