gnu-make

问题 Is there an option to output the "preprocessed" makefile, something equivalent to the GCC's -E option? I have a project comprised of an hierarchy of dozens of modules, each with its makefile. The build is invoked from a master makefile. That master makefile contains includes, variable definitions, command line option dependent variables, etc. So, essentially, I am looking for the processed makefile, including all substitutions. 回答1: Not that I'm aware of. The closest thing you can get to this

问题 I came across this Makefile (found it through an open source project called sendip) I have two confusions regarding this file - Where are .c files being specified as dependencies here? Although all the libraries like ipv6.so , tcp.so are being generated fine, but which line here is responsible for it? I think this is the line ..... Right ?? %.so: %.c $(LIBS) $(CC) -o $@ $(CFLAGS) $(LIBCFLAGS) $+ $(LIBS) but $(LIBS) only specify some .o files. IS this $+ doing something ? 2.I have never heard

问题 Im trying to compile a project with white space into path directories. here you have my Makefile : NAME = ./Release/Online_pricer SRCS = ./Online_pricer/main.cpp \ ./Online_pricer/Currency.cpp \ ./Online_pricer/Curve.cpp \ ./Online_pricer/Environment.cpp \ ./Online_pricer/My_convert.cpp \ ./Online_pricer/My_exception.cpp \ ./Online_pricer/ParserTab.cpp \ ./Online_pricer/Spot.cpp \ ./Online_pricer/Volatility.cpp \ ./Online_pricer/VolatilityCapFloor.cpp \ ./Online_pricer/VolatilitySwaption.cpp

问题 I want to separate the directory with sources from the directory with targets. And it seems that changing the current working directory from Makefile should be the simplest solution. Explicit path to targets is not sufficient because of the following drawbacks: Redundant code in Makefile since every reference to target should be prefixed with variable. More complex command line to build particular intermediate target (worse for debugging). See also Pauls's rule #3: Life is simplest if the

问题 In GNU Make is it possible to have a dependency on a file that includes a % in the filename? I have something like this: foo: results(10%).dat gnuplot config.plt While I can of course choose a different filename it would be nice to know if % should always be avoided or if there is a simple way to escape it (I've tried \ , \\ , and %% with no luck). Edit: My problems seems to be more subtle. It seems to not work because of a combination of matching and a percent filename: all: foo.txt bar.txt

问题 Using GNU's make, I'd like to extract the first character of a variable. Currently I'm using the shell function to have bash perform the substring. I'm wanting to know if there is a way using gmake's built-ins to do the same. DIR=/user/$(shell echo "$${USER:0:1}")/$(USER)/ 回答1: It's not very satisfying, and you'd have to add to $(INITIALS) until you were happy, but: INITIALS := a b c d e f g h i j k l m n o p q r s t u v w x y z U := $(strip $(foreach a,$(INITIALS),$(if $(USER:$a%=),,$a)))

问题 I have noticed that in Implicit Rules in Gnu Make is variable $(TARGET_ARCH) for example : $(LINK.o) $^ $(LOADLIBES) $(LDLIBS) -o $@ LINK.o = $(CC) $(LDFLAGS) $(TARGET_ARCH) I supposed that this variable is needed for cross compilation, but I haven't found any information about it in Gnu Make documentation. 回答1: I agree that it's probably meant for cross-compilation. The variable TARGET_ARCH has no default value - it's there for end-users to define as they see fit. 来源： https://stackoverflow

问题 A common problem I've seen with Makefiles is that executables (and libraries, for that matter) aren't necessarily relinked when the list of dependencies changes. For example: SRCS=$(wildcard *.c) CPPFLAGS=-MMD -MP target: $(SRCS:.c=.o) $(CC) $(LDFLAGS) $^ -o $@ -include $(SRCS:.c=.d) So far, so good: it automatically handles any changes to source files and their included dependencies. If a file is added (because of the wildcard, that means just adding it to the directory, but an explicit list

问题 Consider following make: all: a b a: echo a exit 1 b: echo b start sleep 1 echo b end While running it as make -j2 I receive the following output: echo a echo b start a exit 1 b start sleep 1 make: *** [a] Error 1 make: *** Waiting for unfinished jobs.... echo b end b end We have quite a big make file and it's easy to miss error, since there's no error message at the end of execution. Is there a way for error message to appear also just in the end of the make execution? UPDATE: See my

问题 I'm trying to write a makefile to produce several output files for each of several sources, using pattern rules. I have the following Makefile (GNU Make 3.8.1): all : foo.all bar.all %.all : %.pdf %.svg @echo Made $* %.pdf : touch $@ %.svg : touch $@ .PHONY: foo.all bar.all Since *.all do not represent real output files, I tried marking them as .PHONY. However, running make then doesn't work: $ ls Makefile $ make make: Nothing to be done for `all'. According to make -d : No implicit rule