gnu-make

问题 So I have a makefile with a target dependency like this: all: $(foreach lang, $(LANGS), $(foreach models,$(MODELS),targetName$(model).xml$(lang))) and the targetName target looks like this: targetName%.xml%: MODEL\=% targetName.xml* But it doesn't work. I get this error: make[1]: *** No rule to make target `targetNameMYMODEL.xmlen', needed by `all'. Stop. however, calling 'all' with a hardcoded language in the targetName target like this works: all: $(foreach lang, $(LANGS), $(foreach models,

问题 My first question (yay!) is about gnumake and parallel builds. Here's a quick example file: .PHONY: tool_1 tool_2 tool_3 tool_4 all tools all: | tools tools: | tool_2 tool_3 tool_4 tool_1: # commands for tool 1 tool_2: | tool_1 # commands for tool 2 tool_3: | tool_1 # commands for tool 3 tool_4: | tool_1 # commands for tool 4 If I do make -j on this guy, is what I have here correct to ensure that the commands for tool_1 are executed exactly once, and before make tries to build any of tool_

问题 I have like this in makefile target1: export var1=test $(MAKE) target2 target2: echo $(var1) This is coming as empty I have other depencies so i want to set variable in first target and then all children dependencies should be able to access that EDIT: .ONESHELL: target1: export var1=test echo $(var1) output make target1 export var1=test echo 回答1: By default make invokes a new shell environment for each recipe, the export ed variable on the first line isn't in scope for the second. You can

问题 Consider the following: %.foo: %.bar echo $< > $@ Assuming we have one file 1.bar , the command executed is simply echo 1.bar > 1.foo . However, when % contains a path, rather than just a file name, it start becoming finicky. My problem is that I want to prepend another path to %.bar , the pattern becomes completely mangled. I.e., when %.bar is nice/path/1.bar , this becomes impossible: %.foo: /project/something/%.bar echo $< > $@ This will run, but it executes echo nice/path//project

问题 I want to define a shell function #!/bin/sh test () { do_some_complicated_tests $1 $2; if something; then build_thisway $1 $2; else build_otherway $1 $2; fi } in such a way that I can use it in every rule of my Makefile, such as: foo: bar test foo baz To be clear, I want the shell function to be part of the Makefile. What is the most elegant way to do this? Bonus points if you can do it without calling make recursively. Background: My actual problem is that make -n produces a very long and

问题 I'm not sure if it's gmake or gcc that I don't understand here. I'm using the -MM and -MD options to generate dependency rules for the Unit Testing framework I'm using. Specifically: $(TEST_OBJ_DIR)/%.d: $(TEST_SRC_DIR)/%.cpp @$(CPPC) -MM -MD $< -o $@ @sed -i -e 's|\(.*\)\.o:|$(OBJ_DIR)/\1.o $(TEST_OBJ_DIR)/\1.d $(TEST_OBJ_DIR)/\1.o:|' $@ -include $(TEST_DEP_FILES) When I run make , after all binaries are linked (properly), I see the following extra (unexplained) line before make exits rm

问题 I'm trying to debug a complex Makefile. How do you get GNU make to print all the commands it runs? I couldn't find the answer in the man page (using the -d flag doesn't seem to print it). (This isn't necessary information to answer my question, but in case you're wondering: I'm having trouble compiling a project built on NVIDIA's CUDA library. I can compile it myself, but using their Makefile results in a nasty compiler error. I'd like to use their provided Makefile for easier packaging, and

问题 In a makefile, escaping a new-line with \ allows to split a single-line long string content across multiple source lines. However, the new-line is replaced with a space. Is there a transparent line break in the source that does not affect the string content? VAR=w\ o\ r\ d all: echo $(VAR) The desired output is 'word', but the actual output is 'w o r d'. 回答1: The simplest solution is to use $\<newline> to split the line (at least if you are using GNU Make): VAR = w$\ o$\ r$\ d all: echo $(VAR

问题 I want to make a language depend target. In Particular: I have one source-file and I want to create different Objects which where add to the corresponding language folder. That single source file will differ in the C-Flags, the compiler will get. As long as I used it in a static way, it works quite fine. de/info.o en/info.o es/info.o : info.c $(ECHO) (DEP) $< for $@ Now I thought, it would be great if it is a bit more dynamic, in case i'll add a new language depending file. So I used a

问题 Apart from the fact that bmake is an BSD equivalent of GNU make, I could not clearly understand it's advantages over GNU make. Can anyone help me? I was able to find only one resource that was bit helpful. More help or pointers are appreciated. Thanks, Prabhu 回答1: BSD make and GNU make are both free replacements for the original AT&T make. The major difference is having different syntax for the advanced features. Here is how to put the output of a shell command in a variable in BSD make: #