Variable substitution in Makefile target dependency

问题

I have a Makefile with targets that have associated dependencies. So I use lookup table like:

APPS = a b c

dependency.lookup.a := x
dependency.lookup.b := y
dependency.lookup.c := z

$(APPS): %: path/$(dependency.lookup.%).datafile
    do something with $(dependency.lookup.$@)

This makefile gives me error. *** No rule to make target 'path/.datafile'

Constraints: Only MinGW. can't use shell/MSYS. Also support FreeBSD.

回答1:

This requires using Secondary Expansion feature:

.SECONDEXPANSION:
$(APPS): %: path/$$(dependency.loopup.$$*).datafile
    @echo "$@ depends on $^"

%.datafile : # Create one on demand for testing.
    mkdir -p ${@D}
    touch $@

Outputs:

mkdir -p path/
touch path/x.datafile
a depends on path/x.datafile

Alternatively, use regular dependencies:

a : path/x.datafile
b : path/y.datafile
c : path/z.datafile

$(APPS): % :
    @echo "$@ depends on $^"

The top 3 lines only add dependencies, the rule is specified separately. The output is the same.

回答2:

I had the same problem but with rather long names. I didn't want to repeat them (in APPS = ...), so I used a generated auxiliary makefile.

Makefile:

all: build

include deps.mk
deps.mk: deps.txt deps.sh
    ./deps.sh <$< >$@

build: $(DEPS)
    echo "DEPS are up-to-date."  # or whatever

deps.sh:

#!/bin/bash
echo "# This file is generated by $0"
echo "DEPS ="
while read -r dst src; do
  echo
  echo "DEPS += $dst"
  echo "$dst: $src"
  echo -e '\t''cp $< $@'  # or whatever
done

deps.txt (now only this file needs to be updated for new dependencies):

a x
b y
c z

来源：https://stackoverflow.com/questions/43005281/variable-substitution-in-makefile-target-dependency

标签

makefile

gnu-make