Writing a Makefile rule, for a SINGLE target with MULTIPLE dependacies

问题

For Eg., if I were to compile bunch of files in a hardware description language, I can write a Makefile in the following way

    analyze: a.v b.v c.v top.v
        vcs $(OPTIONS) a.v
        vcs $(OPTIONS) b.v
        vcs $(OPTIONS) c.v
        vcs $(OPTIONS) top.v

Make analyze, will compile all the files in its dependency & builds the final executable. How can I write a "SINGLE Makefile rule", which will compile all its dependencies and build an executable - Mimicking the above with a rule SOMETHING LIKE:

    analyze: %.v
        vcs $(OPTIONS) %.v

The above works for a single file dependency. But, if I have multiple file dependencies how will I handle the multiples files ? Can I use a "for loop" for all the dependencies. I was looking for Makefile options to access the "dependency files" to be used in a for loop, but COULD NOT find one.

回答1:

Use a dummy stamp target for each to-be-analyzed file:

analyze : a.analyzed-stamp b.analyzed-stamp c.analyzed-stamp top.analyzed-stamp

%.analyzed-stamp : %.v
    vcs $(OPTIONS) $<
    touch $@

来源：https://stackoverflow.com/questions/8822591/writing-a-makefile-rule-for-a-single-target-with-multiple-dependacies