verilog

问题 I am relatively new to verilog (a VHDL user), and in order to improve my skills i built my test environment using verilog (my QC use their own env). In my env, I emulate a master that force random stimuli on the lines (i2c master). since i didn't really want to use a real master and wanted only a 'well behaved' master, i created the following macros to provide me with the i2c communications: `define writeChipId(addr)\ sda = 1\ #7500 sda = addr[3];\ #2500 sda = addr[2];\ #2500 sda = addr[1];\

问题 How can one initialize parameter type array in verilog where each of members are 32 bit hexadecimal notation numbers? I have tried the following but it gives me syntax error. parameter [31:0] k[0:63] = {32'habc132, 32'hba324f, ...}; I'm using latest version of iverilog for compiling. 回答1: On EDA Plyground The following example works using modelsim 10.1, the file has a .sv extension, causing it to be interpreted as SystemVerilog: module test; parameter [31:0] k [0:1] = {32'habc132, 32'hba324f}

问题 I have problem with PyHVL. i use PyImport_Import function in my c code. code is built with no errors but function always returns NULL. I saw the same problem and a lot of answers here in this portal, but hardly any solution worked for me. anybody know this? thanks in advance.. here is the function definition. int do_py_initialization(pyhvl_inst_p pp) { PyObject *pName, *pModule, *pDict, *pFunc; PyObject *pArgs, *pValue; char *pyhvl_prerun; if (pyhvl_is_initialized == 0) { if (debugging) { vpi

问题 What will be printed for A and B in the second $display statement? module blocking; reg[0:7] A, B; initial begin A = 3; #1 A = A + 1; B = A + 1; $display("Blocking: A= %d B= %d", A, B ); // A = 4, B = 5 A = 3; #1 A <= A + 1; B <= A + 1; #1 $display("Non-blocking: A= %d B= %d", A, B ); // A = ?, B = ? end endmodule Any pointers on how event scheduling in verilog works with respect to delays and non blocking statements will be really helpful. Thanks. 回答1: because you have #1 before the second

问题 So far I have this code for a 2-bit comparator. module twobitcomparator(xgtyin,xety,xltyin,x1,x0,y1,y0,xgty,xety,xlty); //I/O output xgty, xety, xlty; //xgty - x>y, xlty - x<y, xety - x=y input x1, x0, y1, y0, xgtyin, xetyin, xltyin; //specify circuit behavior assign r = (xgyin); assign s = (xlyin); assign t = (xetyin);//not sure if I need an xetyin assign a = (x1&~y1); assign b = (x1&x0&~y0); assign c = (x0&~y1&~y0); assign xgty = (a|b|c|r);//X>Y assign d = (~x0&~y0); assign e = (x0&y0);

问题 This statement: reg [7:0] register_file [3:0] = 0; Produces this error: Error (10673): SystemVerilog error at simpleprocessor.v(27): assignments to unpacked arrays must be aggregate expressions First of all I am using Verilog, not SystemVerilog, so why is it giving me a SystemVerilog error? Second of all, what is the cause of this error, and how can I fix it? I am using it in my desgin of a very rudementary processor to represent the internal working registers as a multidemmnsional array of

问题 Consider the below code. module TriState ( // Outputs O, // Inouts IO, // Inputs OE, I ); parameter width = 1; input OE; input [width-1:0] I; output [width-1:0] O; inout [width-1:0] IO; assign IO = (OE) ? I : { width { 1'b1 } }; assign O = IO; endmodule // TriState module m1(.a(inout line_P1$IO)); reg val_P1 ; wire line_P1$IO,line_P1$O; TriState #(.width(32'd1)) line_SCL(.I(val_P1), .OE(1), .O(line_P1$O), .IO(line_P1$IO)); always @(*) begin val_P1 <= 1; end endmodule //m1 module m2(.a(inout

问题 I want to implement a reciprical block on Verilog that will later be synthesized on an FPGA. The input should be a signed 32 bit wordlength with a 16 bit fraction length. The output should have the same format. Example input : x ---> output ---> 1/x I have solved the problem using the inbuilt IP core divider. I'm wondering if there is an elegant/altenative way of solving this by for example by bit shifting or 2's complement with some xor grinds. I have used the IP core to implement the

问题 I want to initialize a parameterized array parameter as follow: parameter n = 4; parameter [(log2(n)-1):0] state [(n-1):0] = '{2'h3, 2'h2, 2'h1, 2'h0}; // for n=4 This assignment works fine if n=4. When n=8, it should initialize as {3'h7, 3'h6, 3'h5, 3'h4, 3'h3, 3'h2, 3'h1, 3'h0} I want to initialize it like this: for(i=0,i<n,i=i+1) state[i] = i; Now what should I use to do this initialization? Can I do it with generate? Here log2 is a function. 回答1: First off, you are using SystemVerilog,

问题 I am a newbie in verilog. I have been searching online and most of them suggest to not use for-loop in verilog coding. So is there a better alternative to replace for-loop? The problem that I am facing now is that I need to perform 1 or 2 for-loop in a case statement. And I have been thinking of better alternatives but come up with none. It will be great if any one of you can shed some light on this. Example of my code: always @(*) case (help) 4'd1: for (i=A; i<=20;i=i+B) begin temp[i-1]=1;