How to initialize parameter array in verilog?

问题

How can one initialize parameter type array in verilog where each of members are 32 bit hexadecimal notation numbers? I have tried the following but it gives me syntax error.

parameter [31:0] k[0:63] = {32'habc132, 32'hba324f, ...};

I'm using latest version of iverilog for compiling.

回答1:

On EDA Plyground The following example works using modelsim 10.1, the file has a .sv extension, causing it to be interpreted as SystemVerilog:

module test;
parameter [31:0] k [0:1] = {32'habc132, 32'hba324f};

  initial begin
    $displayh(k[0]);
    $displayh(k[1]);
  end
endmodule

If setting to SystemVerilog does not work or is not available for your simulator I suggest including the syntax error in the question.

来源：https://stackoverflow.com/questions/26300881/how-to-initialize-parameter-array-in-verilog