verilog

问题 solution 1 reg q; always @(posedge clk or negedge rst_n) if (!rst_n) q <= 1'b0; else if (en_a) q <= da; else if (en_b) q <= db; else if (en_c) q <= dc; solution2 reg qw, qr; always @(*) if (en_a) qw = da; else if (en_b) qw = db; else if (en_c) qw = dc; always @(posedge clk or negedge rst_n) if (!rst_n) qr <= 1'b0; else qr <= qw; I use solution 1 a lot and I can find it a lot in many other engineers' code. Solution 2 seperates the combinational logic part and sequencial logic part, the classic

问题 I hope to generate a set of continuous one in verilog like 3 -> 'b111 4 -> 'b1111 5 -> 'b11111 I hope I can use {num{1'b1}} , but I found that the value must be constant. Is there any way in verilog that I can generate the a set of continuous one value? 回答1: Using system verilog you can use the '1 syntax which automatically sizes correctly against the left hand side. Also the above function 2^N - 1 in Dodon Victors answer is just -1 in signed notation. I have shown the usage of both below.

问题 I would like to write a module with a variable number of inputs, i.e. depending on some parameter, the result would be: module my_module #(LENGTH)( input clk, input rst_n, input [LENGTH-1:0] data_1 ); //... endmodule or module my_module #(LENGTH)( input clk, input rst_n, input [LENGTH-1:0] data_1, input [LENGTH-1:0] data_2, input [LENGTH-1:0] data_3 ); //... endmodule Would it be possible to do this in Verilog or Systemverilog or would I have to write a script, let's say in Python, in order

问题 I'm finishing up a project and a requirement is two-way handshaking between functional units inside our processor. I know what it is but is there any 'standard' or a good simple example of it? Only thing I can think of between two units, when there's a data-line between them and when X sends to Y, a separate 'sent' signal is given. When Y receives a 'received' signal is sent to X on another wire. Once X reads that received signal it stops sending data on the data-line and sets sent wire to 0

问题 While inside a module A I'm trying to use the output of a module B as the input of another module C. Essentially this is a "go" switch that is flipped in module B after certain conditions are met and then this is supposed to be the trigger for module C to activate. Is it possible to link an output and input like this? I've been reading around and found this image particularly helpful - however, I don't quite understand the concept of nets or if they will be helpful. Would wiring the output of

问题 I am implementing an FSM controller for a datapath circuit. The controller increments a counter internally. When I simulated the program below, the counter was never updated. reg[3:0] counter; //incrementing counter in combinational block counter = counter + 4'b1; However, on creating an extra variable, counter_next, as described in Verilog Best Practice - Incrementing a variable and incrementing the counter only in the sequential block, the counter gets incremented. reg[3:0] counter, counter

问题 How do I obtain the Verilog language standard? Is there a free version available? If not, what is the closest free resource that I can get? I'm interested in: IEEE Std 1364-2001 IEEE Std 1364-2005 I found paid versions on IEEEXplore, but the price ($175) seems a bit steep for someone who just wants to look up a couple things. 回答1: The closest you can get for free is the IEEE 1800-2012 SystemVerilog LRM, which you can download for free here: http://standards.ieee.org/getieee/1800/download/1800

问题 I'm trying to make a morse code display using an led. I need a half second pulse of the light to represent a dot and a 1.5 second pulse to represent a dash. I'm really stuck here. I have made a counter using an internal 50MHz clock on my FPGA. The machine I have to make will take as input a 3 bit number and translate that to a morse letter, A-H with A being 000, B being 001 and so on. I just need to figure out how to tell the FPGA to keep the led on for the specified time and then turn off

问题 In the following code, I am storing the history of buttons player 1 and player 2 pressed. The code compiles without errors but has warnings. I am unable to solve these warnings. I am posting the code here. module game(clk50,red,green,blue,hsync,vsync, button,led); input [8:0] button; input clk50; output red; output green; output blue,led; output hsync; output vsync; // divide input clock by two, and use a global // clock buffer for the derived clock reg clk25_int; always @(posedge clk50)

问题 I am now doing reading input data from txt file and write the results into txt file. However the results runs in the simulation works well but it fail to link back the the conv module which is o = a+b; the system able to read the values in x.txt and d.txt but cannot link it back to a and b. What is my mistake and how to correct it? And from the same cases in i found out that the system cannot write out negative decimal value although it is change to "%d\n" in $fwrite. Any method to solve that