how to generate a set of continuous one in verilog

问题

I hope to generate a set of continuous one in verilog like

3 -> 'b111
4 -> 'b1111
5 -> 'b11111

I hope I can use {num{1'b1}}, but I found that the value must be constant. Is there any way in verilog that I can generate the a set of continuous one value?

回答1:

Using system verilog you can use the '1 syntax which automatically sizes correctly against the left hand side.

Also the above function 2^N - 1 in Dodon Victors answer is just -1 in signed notation. I have shown the usage of both below.

Some simulators may not work correctly with widths greater than 32, although I believe all modern simulators have fixed this issue.

Example below on EDAPlayground:

module dut;

  logic [65:0] test1;
  logic [65:0] test2;

  initial begin
    #1ps;
    test1 = '1;
    test2 = -1;

    #1ps;
    $displayb(test1);
    $displayb(test2);
  end
endmodule

Output:

# 111111111111111111111111111111111111111111111111111111111111111111
# 111111111111111111111111111111111111111111111111111111111111111111

回答2:

N continuous 1 is just 2^N - 1, so you can use:

module test;
  initial begin
    $display("%b", ('b1 << 1) - 'b1);
    $display("%b", ('b1 << 2) - 'b1);
    $display("%b", ('b1 << 3) - 'b1);
    $display("%b", ('b1 << 4) - 'b1);
    $display("%b", ('b1 << 5) - 'b1);
  end
endmodule

and the output:

You can use a function to generate like this:

function [31:0] gen1;
    input [5:0] n;
begin
    gen1 = ('b1 << n) - 1;
end
endfunction

then just call it using gen1(10).

回答3:

How about this: ~('1 << n)

Test module:

module test;
  logic [7:0] a1=~('1 << 1) ;
  logic [7:0] a2=~('1 << 2) ;
  logic [7:0] a3=~('1 << 3) ;
  initial begin

    $display("%b", a1 );
    $display("%b", a2 );
    $display("%b", a3 );
  end
endmodule

来源：https://stackoverflow.com/questions/23239366/how-to-generate-a-set-of-continuous-one-in-verilog

标签

verilog