Output of a module used as input of another in verilog

问题

While inside a module A I'm trying to use the output of a module B as the input of another module C. Essentially this is a "go" switch that is flipped in module B after certain conditions are met and then this is supposed to be the trigger for module C to activate. Is it possible to link an output and input like this?

I've been reading around and found this image particularly helpful - however, I don't quite understand the concept of nets or if they will be helpful. Would wiring the output of module B to a reg that's used as input to module C work? Thanks.

EDIT:

I'm looking for something like this (involving 3 different modules) where I'm instantiating a module B and a module C within a module A. I want to connect B's output to C's input.

回答1:

you can make those connections For example:

module my_moduleA (inA, outA)
input inA;
output reg outA; //If you want to assign something to out inside an always block, it has to be output reg, otherwise you will have to use assign out from an always block.

//Put your logic here

endmodule

module my_moduleB (inB, outB)
input inB;
output reg outB; //If you want to assign something to out inside an always block, it has to be output reg, otherwise you will have to use assign out from an always block.

//Put your logic here

//Instantiation of module A
my_moduleA instance(  //Here is the connection made between module A and B
.inA (inB),  
.outA (outB));
endmodule

This is how the connections are made, if you want to make those connections on internal signals, then you can use wire type

回答2:

Your three modules example (image), using wire outB_to_inC to connect output to input:

//A.v
module A(inA, outA);
input wire inA;
output wire outA;

wire outB_to_inC;

B B_inst(.inB(inA), .outB(outB_to_inC));

C C_inst(.inC(outB_to_inC), .outC(outA));

endmodule

/////

//B.v
module B (inB, outB);
input wire inB;
output wire outB;

//... more code here

endmodule

/////

//C.v
module C (inC, outC);
input wire inC;
output wire outC;

//... more code here

endmodule

来源：https://stackoverflow.com/questions/19327819/output-of-a-module-used-as-input-of-another-in-verilog

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verilog