verilog

问题 I am new in Verilog and I am trying to implement single precision floating point addition-subtraction using verilog. I am getting an error which I am unable to correct. Can anyone please help me? module addModule(Rs,Re,Rm,As,Ae,Am,Bs,Be,Bm); //Declarations of ports Rs,Re,Rm; As,Bs; input [7:0] Ae,Be; input [22:0] Am,Bm; reg [7:0] Re; reg [22:0] Rm; reg Rs; //wire declarations. wire [23:-1] C; assign C[-1] = 0; wire [23:1] sum; //variable declaration. genvar count; always @(*) begin //Add two

问题 As I wrote in my previous post Synthesizable array of XY values I wanted to create an array in Verilog to store x , y values of a given function. Now I want to compare an input with x values of this array. If the value is within a specific region I want to save the index of this region and perform an addition with y with the same index. The result goes to the output. The code compiles just fine but its not synthesizes any circuit. The idea later is to use this array to perform linear

问题 So I need to get sinus waveform. In cases I have wrote values of x and y axis in range of 2pi how to get the waveform of the sinus in this range? module sinus1(in,clk,res,out); input clk,res; input [7:0]in; output reg [7:0]out; always @(posedge clk) if (res) case (in) 8'b00000000: out<=8'b10000000; 8'b00000001: out<=8'b10000011; 8'b00000010: out<=8'b10000110; 8'b00000011: out<=8'b10001001; 8'b00000100: out<=8'b10001100; 8'b00000101: out<=8'b10001111; 8'b00000110: out<=8'b10010010; ... ... ...

问题 I am trying to debug my code shown below. I am fairly new to SystemVerilog and hopefully I can learn from this. Let me know of any suggestions. The errors I am receiving are: Error-[ICPD] Invalid procedural driver combination "divide.v", 2 Variable "Q" is driven by an invalid combination of procedural drivers. Variables written on left-hand of "always_comb" cannot be written to by any other processes, including other "always_comb" processes. "divide.v", 2: logic [7:0] Q; "divide.v", 8: always

问题 This may seem like a rather stupid question, but the transition from software to HDL's is sometimes rather frustrating initially! My problem: I have an array multiplication I am trying to accomplish in Verilog. This is a multiplication of two arrays (point by point) which are of length 200 each. The following code worked fine in the testbench: for (k=0; k<200; k=k+1) result <= result + A[k] * B[k]; But it doesn't even come close to working in the Verilog module. I thought the reason was

问题 Is there a way in Verilog or SystemVerilog to insert generate statement inside case statement to generate all the possible input combinations. For example a typical use case would be for a N:1 mux. case(sel) generate for(i = 0; i < N; i += 1) i: out = q[i]; endgenerate endcase I tried this, but the tool gives error. An alternate syntax is available which is out <= q[sel]; But, my tool is not understanding this(the mux is fully decoded) and generating combinational loops. I can use if

问题 I wrote the following code for BCD to seven segment. The code compiles find and simulates too but the value of num is not going beyond 2. I don't know why is that. Here is the code: module BCDtoSeven_TOP reg [3:0] num; wire a,b,c,d,e,f,g; BCDtoSeven s(num,a,b,c,d,e,f,g); initial begin num=1; end always @(num<=9) begin #2 num=num+1; end endmodule Sub Module: module BCDtoSeven(num,a,b,c,d,e,f,g); output a,b,c,d,e,f,g; input [3:0] num; assign a=(num==4 || num==5 || num==6 || num==7 || num==8 ||

问题 I am new to Verilog so I am having some problems working with if Basically I have a 5 bit number, and a want to split it so I can have a 2 digits decimal number. For doing so I have this piece of code reg [4:0] position, aux; reg [3:0] display1, display2; reg [2:0] secondDigit; always @(negedge iKEY[1] or negedge iKEY[2]) begin aux = position; for(secondDigit = 2'b0; aux >= 5'b01010; secondDigit = secondDigit + 2'b01) aux = aux - 5'b01010; assign display1 = aux[3:0]; assign display2 = {2'b0,

问题 I have inputs like this coming into a module: input wire [31:0] row0_Q, input wire [31:0] row1_Q, ... input wire [31:0] row30_Q, input wire [31:0] row31_Q and want to form busses of the "columns" for lack of better terms. I can do it the long way: assign col31 = {row31[31], row30[31], ... row1[31], row0[31]} ; but it's a lot of typing. Is there an easier way? 回答1: There is no easy way within Verilog. Try creating a script to generate the code for you. You can have the code generated by your

问题 I would like to convert the following VHDL code into Verilog. But I ran into some problems as I mentioned herecompilation error. Could some one give me some hints of how to properly write the same function in Verilog? Thank you! library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.classic_multiplier_parameters.all; entity poly_multiplier is port ( a, b: in std_logic_vector(M-1 downto 0); d: out std_logic_vector(2*M-2 downto 0) );