verilog

问题 The code for the FSM which involves particular delay to be executed before moving to another state is as shown below: module INIT_FSM(sys_DLY_100US,sys_CLK,sys_INIT_DONE,iState,sys_RESET); input sys_DLY_100US; input sys_CLK; inout sys_INIT_DONE; output [4:0] iState; input sys_RESET; wire sys_DLY_100US,sys_CLK; reg [4:0] iState; wire sys_INIT_DONE; reg [4:0] NextState; parameter i_NOP=5'b00000; parameter i_PRE=5'b00001; parameter i_tRP=5'b00010; parameter i_AR1=5'b00011; parameter i_tRFC1=5

问题 I have designed a 16*16 Montgomery multiplier. The code uses a 16*16 multiplier to perform three multiplications. The multiplications are performed one after the other using the same multiplier and the result of each multiplication is stored in the registers. The single 16*16 multiplier performs at a frequency of about 1550 MHz, but the frequency of the Montgomery multiplier (which uses a single 16*16 multiplier three times) is reduced to almost 500 MHz when the three multiplications are

问题 I'm new in Verilog and i have question that i don't understand: module my_func(t0, t1, t2, t3, s0, s1, res) begin in t0, t1, t2, t3, s0, s1; out res; always begin if ( s0=0 && s1=0 ) res = t0; if ( s0=1 && s1=0 ) res = t1; if ( s0=0 && s1=1 ) res = t2; if ( s0=1 && s1=1 ) res = t3; end endmodule module my_FSM( input, output ) begin in input; out output; ¬¬__(1)__ d[3]; __(2)__ q[3]; always @ (in) begin d[0] = input | q[2]; d[1] = input & q[0]; my_func(0, q[0], q[1], q[2], q[1], input, d[2]);

问题 I have seen the following used to make state changes in Verilog modules: state <= 2'b10; state <= #1 IDLE; Why is <= used and not just =? What is the purpose of using #1? Does it make a difference? Here is some Verilog code for a FSM that shows the first one being used. Would it work the same if it was replaced with the second? module fsm( clk, rst, inp, outp); input clk, rst, inp; output outp; reg [1:0] state; reg outp; always @( posedge clk, posedge rst ) begin if( rst ) state <= 2'b00;

问题 I am trying to write a top verilog with instansiations of a few identical modules. the first instansiation should be connected outside, while the other instansiations should be floating. Can anyone help me use the AUTO's with AUTO_TEMPLATE to have emacs connect all inputs to zero, and leave all outputs empty []. I don't have any identification in the module IO name indicating if its input or output (so I can't use wildcards) Is there a way that the tool can identify all inputs (and connect to

问题 I am new to verilog. I am writing the code for a 10x16 Round-Shift register. Can you help me with the error and also if any optimizations can be done? module shift_reg_v( output [15:0] word_out ); integer i; integer j; reg [159:0] coeff; reg [15:0] word; initial begin for (i=0;i<160;i=i+1) begin coeff[i] = 0; end for (i=0;i<16;i=i+1) begin word[i] = 0; end end always begin for (j=0;j < 10;j = j+1) begin for (i=0;i < 16;i = i+1) begin if (j==0) begin word[i] = coeff[(16*(j+1))+i]; end else

问题 I am new to verilog and have a doubt concerning the race conditions in the following code which is taken from FPGA Prototyping by Veriloog Examples by Pong P. Chu. The code is: always @(posedge clk) a = b; always @(posedge clk) b = a; This will infer races depending on which always block gets executed first. But always blocks should get executed in parallel. Correct me if I am wrong. I know there is blocking assignment but how does it affect the first statement of the block, which is the

问题 I want to compile this Verilog code but i had error in instance of B module in MultiP module. error 1: Undefined variable B. error 2: near "Adder1": syntax error, unexpected IDENTIFIER. Code: module A(x,y,ci,co,sum); input x,y,ci; output co,sum; reg co,sum; always @(x | y | ci) begin sum = x ^ y ^ ci; co = (x & y) | (ci & y ) | (ci & x); end endmodule module B(ppk,x,y,ci,co,ppko); input x,y,ppk,ci; output ppko,co; reg ppko,co; always @(x | y | ci | ppk) begin A((x & y),ppk,ci,co,ppko); end

问题 I have basic binary math question. For example; reg [31:0] a = 32'hFFFF_FFFF; reg [31:0] b = 32'hFFFF_FFFF; reg [31:0] c = 0; I know c = a - b will result in zero and overflow flag will not be set. My understanding is that ALU uses 2's complement of subtrahend (right side of operator) and adds it to minuend (left side of operator). So 2s complement for value stored in reg b is 32'h1. Now, if I add this to reg a, I will get 32 zeros and a 1, which is overflow. Then why is not overflow flag set

问题 I am trying convert a signed floating number in Verilog to a signed 24 bit binary value. For example -0.0065 would become: 24'b100000000110101001111110 0.0901 would become: 24'b000001011100010000110010 Is this correct? Thank you 回答1: Taking the fractional decimal 0.0901 and converting to a fixed-point value with 2 integer bits and 22 fractional bits (24 bit total): Ruby syntax used for the maths (you can cut and paste into irb (interactive ruby) a command line tool): i = (0.0901 * 2**20) #