verilog

问题 In verilog I have an error that I can't get past. this is the first bit of the code then the last bit module Decoder(op,funct,aluop,mwr,mreg,mrd,alusrc,regdst,regwr,btype); input[5:0] op,funct; output[2:0] aluop; output[1:0] btype; output mwr,mreg,mrd,alusrc,regdst,regwr; wire aluop,mwr,mreg,mrd,alusrc,regdst,regwr,btype; case(op) 6'b000000: begin case(funct) 6'b001010: assign aluop = 3'b010; 6'b001100: assign aluop = 3'b111; 6'b010001: assign aluop = 3'b011; default: assign aluop = 3'b000;

问题 I'm trying to instantiate some modules in Verilog using a generate block since I'm going to be instantiating a variable amount of them. genvar i; generate for (i=1; i<=10; i=i+1) begin status whatever_status ( .clk(clk), .reset_n(reset_n), .a(a[i]), .b(b[i]), .out(out[i]) ); end endgenerate a & b are declared as input arrays to the parent module and out is declared as a array of wires. What am I doing wrong here? Is this not allowed in Verilog? Quartus is telling me: Error (10644): Verilog

问题 My code is a sequential structure, 8 constant taps, 8 bit FIR. I used a memory to save all the input*taps, but I keep getting and error while trying to save these multiplications. I compiled it on Modelsim and got "syntax error". After, I tried iverilog and got "syntax error" and "error: Invalid module instantiation". I feel like I'm missing something really obvious but couldn't solve it. The code goes as follows: /* Código de um filtro FIR 8 taps, 8 bits Aluno: Rafael Menezes Start date: 19

问题 I'm new to Verilog and I'm trying to create a 4-bit binary Random Number Generator. The program is as follows, could anyone help me by mentioning the errors? I initially tried out this: module rng (d); inout[3:0]d; //wire[3:0]d; //input clk, rst; //wire [3:0] w; dff f1(a[0],clk,d[0],rst); dff f2(a[1],clk,d[1],rst); dff f3(a[2],clk,d[2],rst); dff f4(a[3],clk,d[3],rst); xorper p(d[0],d[1],d[2],d[3],a[0],a[1],a[2],a[3]);//permutations //dff f1(a,clk,q,rst); dff x(d,clk,q,rst); endmodule I also

问题 I'm trying to implement the following Sequential Circuit in Verilog (Modelsim 10.4a) Here's the code I'm using seq_circuit1.v module seq_circuit1(x, clk, Q0, Q1); input x, clk; output Q0, Q1; reg J0,K0,J1,K1; always @(negedge clk) begin //Blocking and Non Blocking both will work J0 = Q1 & ~x; K0 = Q1 & x; J1 = x; K1 = (Q0 & x) || (~Q0 & ~x); jkfflop JKff0 (J0,K0,Q0); jkfflop JKff1 (J1,K1,Q1); end endmodule jkfflop.v module jkfflop(J,K,clk,Q); input J,K,clk; output Q; if(J==0 & K==1) begin

问题 Hello Friends I still not know how to Generate Delay in Verilog For synthesis and call it any line in Verilog for synthesis...for finding this I write a code but it not works please help me if you know how to Generate Delay and call in any line like a C's Function* ......Actually Friends if you tell me why I use for Loop here then my answer is - I want to move pointer inside for loop until and unless they completes its calculation that I made for Delay Generation .. module state_delay; reg

问题 I have used inout with c but for c to be on the LHS of procedural assignment, it needs to be a reg type variable. Can anyone help me out with this code? module multiedgeclk(input clk ,[7:0] a,b,d, inout [7:0] c, output reg [7:0]f); always @(posedge clk) c <= a + b; always @(negedge clk) f = c & d; endmodule 回答1: In verilog inout is the direction of the port. wire or reg is the type of the signal. If you want to drive a bi-directional port, it should be declare as inout wire or inout and drive

问题 Closed. This question is off-topic. It is not currently accepting answers. Want to improve this question? Update the question so it's on-topic for Stack Overflow. Closed 4 years ago . I am not familiar with verilog. I did my best trying to convert it. While simulating the clock is going from '0' to 'x' which is weird. I am suspecting this part to be the problem repeat(9) @(posedge clk); DataIn_i <= 1'b1; DataIn_q <= 1'b1; @(posedge clk); FillSel <= 1'b0; DataIn_i <= 1'b0; DataIn_q <= 1'b0;

问题 would an always block with no sensitivity list infer a combinational logic, just the same as always_comb or always @(*) ? Eg code: always begin if (sig_a)begin @(posedge sig_b); // wait for a sig_b posedge event @(negedge sig_b); // then wait for a sig_b negedge event event_true=1; end if (event_true)begin @((sig_c==1)&&(sig_a==0)); //wait for sig_a to deassert and sig_c assert event to be true yes =1; end else yes =0; end 回答1: Synthesis tools require a specific template coding style to

问题 I am trying to convert from Hex To BCD in verilog. I am not using any clocks or other stuff. In my program, I give one input at a time and convert it and show the result. But my program is giving undefined result. How can I fix it? Any solution? module HexToBCD(num,result); input num; output [7:0]result; assign result[0]=num%2; assign num=num/2; assign result[1]=num%2; assign num=num/2; assign result[2]=num%2; assign num=num/2; assign result[3]=num%2; assign num=num/2; assign result[4]=num%2;