Verilog Random Number Generator

问题

I'm new to Verilog and I'm trying to create a 4-bit binary Random Number Generator. The program is as follows, could anyone help me by mentioning the errors?

I initially tried out this:

module rng (d);
 inout[3:0]d;
 //wire[3:0]d;
 //input clk, rst;
 //wire [3:0] w;

 dff f1(a[0],clk,d[0],rst);
 dff f2(a[1],clk,d[1],rst);
 dff f3(a[2],clk,d[2],rst);
 dff f4(a[3],clk,d[3],rst);

 xorper p(d[0],d[1],d[2],d[3],a[0],a[1],a[2],a[3]);//permutations
 //dff f1(a,clk,q,rst);
 dff x(d,clk,q,rst);
endmodule

I also tried out this:

module re(b,q,clk,rst);
 input [3:0]q;
 input clk,rst;
 wire [3:0]q,a;

 output [3:0]b;
 reg [3:0]b;


 rox f1(q[0],q[1],q[2],q[3],a[0],a[1],a[2],a[3]);//permutations
 rod f2(a,clk,b,rst);//dff
 always@(posedge clk) begin
 if (rst==1'b0) begin
  b[0]=q[0];
  b[1]=q[1];
  b[2]=q[2];
  b[3]=q[3];
 end else if(rst==1'b1)
  b[0]=1'bx;
  b[1]=1'bx;
  b[2]=1'bx;
  b[3]=1'bx;
 end

endmodule

回答1:

I would suggest starting with an LFSR for random number generation. They are a straight forward shift register, with taps back to a mutlibit XOR to create the feedback bit.

Your implementation of a flop could be better.
1) Add negedge rst to the sensitivity list
2) You do not want to assign x's
3) use non-blocking assignments (<=)

reg [3:0] b;

//LFSR feedback bit
wire feedback
assign feedback = b[0] ^ b[3];

// Add active low reset to sensitivity list
always@(posedge clk or negedge rst) begin
 if (rst==1'b0) begin
  b[3:0]<=4'hF;  //reset condition first
 end 
 else begin
  b[0]<=feedback;
  b[1]<=b[0];
  b[2]<=b[1];
  b[3]<=b[2];
  //Alternative Verilog might be
  // b = {b[2:0], feedback};
 end

For choosing tap point for an LFSR search for a maximal length LFSR. A maximal LFSR will have the longest number sequence before it repeats for a given length of register and tap points.

来源：https://stackoverflow.com/questions/12632734/verilog-random-number-generator

标签

verilog