Unknown verilog error 'expecting “endmodule”'

问题

In verilog I have an error that I can't get past. this is the first bit of the code then the last bit

 module Decoder(op,funct,aluop,mwr,mreg,mrd,alusrc,regdst,regwr,btype);
  input[5:0] op,funct;
  output[2:0] aluop;
  output[1:0] btype;
  output mwr,mreg,mrd,alusrc,regdst,regwr;
  wire aluop,mwr,mreg,mrd,alusrc,regdst,regwr,btype;
  case(op)
      6'b000000: begin
          case(funct)
              6'b001010:
                  assign aluop = 3'b010;
              6'b001100:
                  assign aluop = 3'b111;
              6'b010001:
                  assign aluop = 3'b011;
              default:
                  assign aluop = 3'b000;          
          endcase
          assign btype = 2'b00;
          assign mwr = 1'b0;
          assign mreg = 1'b0;
          assign mrd = 1'b0;
          assign alusrc = 1'b0;
          assign regdst = 1'b1;
          assign regwr = 1'b1;
          end

...

  default: begin
      assign aluop = 3'b000;
        assign mwr = 0;
        assign mreg = 0;
        assign mrd = 0;
        assign alusrc = 0;
        assign btype = 2'b00;
        assign regdst = 0;
        assign regwr = 0;
        end
endcase

endmodule

it keeps giving me the following errors

Error (10170): Verilog HDL syntax error at Decoder.v(7) near text "case"; expecting "endmodule" Error (10170): Verilog HDL syntax error at Decoder.v(14) near text "6"; expecting "endmodule"

It also does this at every end statement and default and endcase

I have no idea why it's doing this, I'm fairly new to verilog.

thanks in advance

回答1:

I believe you're only allowed to use a case statement or if/else inside of an always block. I'm not sure why your error message doesn't say something a little more helpful, but that is likely to be the problem.

Try rewriting your code like the following:

//change wire types to reg type

always @*
begin
  case (op)
    6'b000000: begin
      aluop = 3'b000
    end
    ...
  endcase
end

回答2:

This is a guess, but the compiler is complaining because it is likely expecting IEEE 1364-2001 verilog and your code isn't valid for this version of the language. In any case, Tim's code is probably the functionality you're looking for.

As to why it isn't valid, Verilog contains essentially two 'contexts' inside every module declaration. Anything that appears directly in the module is a module item. These include reg/wire declarations, assign statements, always statements, generate constructs and module instances.

module mod;

reg reg1;           //Module item
wire wire1;         //Module item
assign wire1 = 0;   //Module item
always reg1 = 0;    //Module item
parameter con1 = 0; //Module item
 //Instances a different module based on con1
case(con1)          //Module item
  0:mod2 inst1(reg1);
  1:mod3 inst1(reg1);
  2:mod4 inst1(reg1);
endcase

endmodule

Second, there are procedural contexts in which there can be procedural statements. This is any code inside a task declaration, function declaration, always block, initial block and a few other areas.

module mod2;
reg a;

always
  begin
  a = 0; //Procedural statement
  end

initial
   a = 0; //Procedural statement 

function func1(input arg1);
case (arg1) //Procedural statement 
  0:func1 = 0; 
  default:func1 = 9;
endcase
endfunction

endmodule

Since 2001, Verilog contains two types of case statements, procedural case statements and generate case statements. Procedural case statements work just like they do in procedural languages but must appear in a procedural context. Generate case statements are evaluated statically before simulation starts and may only appear in a module declaration context as a module item. Note that the second context requires the case expression to be constant.

In the latest version of verilog, 1364-2005, a generate case may appear directly in the module scope however in the 2001 version of the language any generate item must be surrounded with generate..endgenerate keywords. If your compiler is expecting IEEE 1364-2001 then the error message you see makes sense.

来源：https://stackoverflow.com/questions/10443368/unknown-verilog-error-expecting-endmodule

标签

verilog