verilog

问题 Is it possible and/or useful to ever use a continuous assignment in a Verilog procedure? For example, would there ever be any reason to put an assign inside of an always block? For example this code: always @(*) begin assign data_in = Data; end Furthermore would it be possible to generate sequential logic with this approach? always @(posedge clk) begin assign data_in = Data; end 回答1: It is called procedural continuous assignment . It is the use of an assign or force (and their corresponding

问题 Is it possible and/or useful to ever use a continuous assignment in a Verilog procedure? For example, would there ever be any reason to put an assign inside of an always block? For example this code: always @(*) begin assign data_in = Data; end Furthermore would it be possible to generate sequential logic with this approach? always @(posedge clk) begin assign data_in = Data; end 回答1: It is called procedural continuous assignment . It is the use of an assign or force (and their corresponding

问题 I am trying to write a task that gives a variable paddr diffrent values: module paddr1 ; task paddr1; input [10:0]paddr; input clock; @(posedge clock) begin paddr=10 #100; paddr=20; #100; paddr=30; #100; paddr=40; #100; paddr=50; #100; paddr=60; #100; paddr=70; #100; paddr=80; #100; end endtask endmodule I tried to call this task from test bench and wrote: paddr1 (paddr,clock); It passes compilation But when I'm trying to run simulation I get an eror massage: Unresolved reference to 'paddr1'.

问题 I am trying to copy a 2d array into another like so: reg [11:0] input_matrix [0:array_width - 1] [0:array_height - 1]; reg [11:0] output_matrix [0:array_width - 1] [0:array_height - 1]; always @(posedge clk) begin if(<some condition>) output_matrix <= input_matrix; end So, we have two 2D arrays of 12-bit values. I'd like to copy one into the other. This doesn't seem to be possible. Does anyone know the correct way to do this? Or, if not, explain why it's not possible? I can't see any reason

问题 I am attempting to program an addition and subtraction program in Verilog. Problem is Implementation and testing in Verilog of a module that performs Addition or Subtraction, then a Mux chooses between letting go through the result of one or the other, and then Decode the selected result from binary into a 7-segment Display format. Verilog Module will have 3 inputs: two 4-bit inputs named A and B, and a select input S. Your circuit should add the two numbers and should also subtract B from A

问题 From the code mostly from the sample of myhdl: from myhdl import Signal, intbv, delay, always, now, Simulation, toVerilog __debug = True def ClkDriver(clk): halfPeriod = delay(10) @always(halfPeriod) def driveClk(): clk.next = not clk return driveClk def HelloWorld(clk, outs): counts = intbv(3)[32:] @always(clk.posedge) def sayHello(): outs.next = not outs if counts >= 3 - 1: counts.next = 0 else: counts.next = counts + 1 if __debug__: print "%s Hello World! outs %s %s" % ( now(), str(outs),

问题 I want to execute always block at time zero. For e.g. below code won't execute at time zero. always @* begin //functional code end I moved sensitivity list at the end so that code will execute at time zero, always begin //funcitonal code @*; end This code executes at time zero but does not execute at all after time zero, even if there is a change in inputs used inside the block. For example see the code below and its output: module AlwaysTimeZeroTest_v(); reg reg_A; initial begin $display ("I

问题 I made some tests in some EDA playground, to check what simulator tools are reporting when in a module some inputs are driven. Here is eda playground link : https://www.edaplayground.com/x/5qK4 So from my experiment the only way the tool is reporting some error when doing such thing is using the var keyword when defining the input. Can someone explain why there is difference between the three different way to declare the input ? I guess that means you can do port coercion when declaring it as

问题 The following verilog source code and/or testbench works nicely across commercial simulators, iverilog as well as formal verification tool (yosys-smtbmc) Please keep the complaint about `ifdef FORMAL until later. I need them to use with yosys-smtbmc which does not support bind command yet. I am now debugging the generate coding since the multiplication (using modified baugh-wooley algorithm) does not work yet. When o_valid is asserted, the multiply code should give o_p = i_a * i_b = 3*2 = 6

问题 Recently I've came across following issue: in Quartus software I've defined my Verilog module as follows: module module_name( input [w1-1:0] in1, input [w2-1:0] in2, output [w1-1:0] out1 ); parameter w1 = 16; parameter w2 = 8; ... endmodule This module compiled without any issues. But, when I tried to simulate that code in Modelsim(-Altera) 10.3d, I got following errors: (vlog-2730) Undefined variable: 'w1'. (vlog-2388) 'in1' already declared in this scope (module_name) (vlog-2730) Undefined