verilog

问题 I'm getting the error [Synth 8-2576] procedural assignment to a non-register result is not permitted ["lpm_mult.v":29] What am i doing wrong? module lpm_mult ( dataa, datab, // multiplicand,multiplier sum, // partial sum clock, // pipeline clock clken, // clock enable aclr, // asynch clear result // product ); input clock; input clken; input aclr; input [31:0] dataa; input [31:0] datab; input [63:0] sum; output [63:0] result; always @ (clken or posedge clock) begin if (1==clken) begin assign

问题 I am trying to create a module which switches x input data packets to a single output packet according to a one hot input. If x was a fixed value of 4, I would just create a case statement, case (onehot) 4'b0001 : o_data = i_data[0]; 4'b0010 : o_data = i_data[1]; 4'b0100 : o_data = i_data[2]; 4'b1000 : o_data = i_data[3]; default : o_data = 'z; endcase But with variable x, how do I define all cases? Thanks. 回答1: parameter X = 4; input [X-1:0] onehot; input i_data [X]; output reg o_data;

问题 I saw some statements in the form of below. What does #`DEL mean here? I just have basic understanding on verilog, and cannot find its meaning easily because it contains special character. cmd <= #`DEL 32`b0 回答1: It is a delay statement. Delaying the assign of value on the Righthand side to the lefthand side by the defined amount, in this case delaying cmd becoming zero. The delay can be specified in any time or realtime format, #1 would be 1 timestep as defined by the ... #1ns, #1us, #1ms

问题 I've got a register declared as so: logic signed [15:0][2:0][15:0] registers; When I place a 2's compliment number into the array and arithmetically shift the number, it logical shifts instead: registers[0][0] = 16'b1000000000000000; registers[0][0] = registers[0][0]>>>2; Apparently, the system will logical shift instead of arithmetically shift if the number is not signed. However as you can clearly see, 'registers' is definitely signed. Does anybody know what I might be missing here? Thanks!

问题 I've got a register declared as so: logic signed [15:0][2:0][15:0] registers; When I place a 2's compliment number into the array and arithmetically shift the number, it logical shifts instead: registers[0][0] = 16'b1000000000000000; registers[0][0] = registers[0][0]>>>2; Apparently, the system will logical shift instead of arithmetically shift if the number is not signed. However as you can clearly see, 'registers' is definitely signed. Does anybody know what I might be missing here? Thanks!

问题 Can we have an array of instances for a custom module? For example: we can have input [15:0] a; - this creates a bus. Can we do same thing for custom modules, i.e. DFF [15:0] d; , where DFF is a custom module? Here I intend to create 16 instances of the DFF module. 回答1: Verilog arrays of instances were added in Verilog-1995 (IEEE 1364-1995). They can be used with gates, user-defined primitives, and modules. Generates, which are more powerful but also more complex, were added in Verilog-2001.

问题 I want to create a 64-bit barrel shifter in verilog (rotate right for now). I want to know if there is a way to do it without writing a 65 part case statement? Is there a way to write some simple code such as: Y = {S[i - 1:0], S[63:i]}; I tried the code above in Xilinx and get an error: i is not a constant. Main Question: Is there a way to do this without a huge case statment? 回答1: I've simplified some of the rules for clarity, but here are the details. In the statement Y = {S[i - 1:0], S[63

问题 Is it possible to write a function that can detect the input data width automatically? For example, consider the parity function below: function parity; input [31:0] data; parity = ^ data; endfunction When parity(data) is called, the input data should be limited to 32 bits. Alternatively, one could write a macro, such as `PARITY(data) in which the system function $bits can detect the width of data and make the macro width-independent. Is it possible to have the same flexibility for functions?

问题 How do you implement a hardware random number generator in an HDL (verilog)? What options need to be considered? This question is following the self-answer format. Addition answers and updates are encouraged. 回答1: As noted in Morgan's answer this will only produce a single random bit. The number of bits in the LFSR only set how many values you get before the sequence repeats. If you want an N bit random number you have to run the LFSR for N cycles. However, if you want a new number every

问题 I'm trying to get a module to pass the syntax check in ISE 12.4, and it gives me an error I don't understand. First a code snippet: parameter ROWBITS = 4; reg [ROWBITS-1:0] temp; genvar c; generate always @(posedge sysclk) begin for (c = 0; c < ROWBITS; c = c + 1) begin: test temp[c] <= 1'b0; end end endgenerate When I try a syntax check, I get the following error message: ERROR:HDLCompiler:731 - "test.v" Line 46: Procedural assignment to a non-register <c> is not permitted. I really don't