verilog

问题 I'm in the process of implementing a finite state machine in verilog, and I've encountered an issue. However, I know what the problem is, but I'm not sure how to fix it. This is my current code: module moore_SM(clk, rstn, btn, z, rstLED, state); //Port Assignments input clk, rstn; input [2:0] btn; output z; output reg rstLED; output reg [5:0] state; //Internal Port Assignments reg [1:0] w, x; //NOTE: This is typically the input in FSM, //but it is internal because there is a conversion from

问题 Can I use a wire inside an always block? Like for example: wire [3:0]a; assign a=3; always @(c) begin d=a+c; end It got compiled without throwing any error. Why? 回答1: Yes, you can use a wire's value inside an always block, you just can not assign a value to a wire in always or initial block. The only real difference between a wire and reg is the syntax for assigning values. In the above example d could also have been created as a wire, these are equivalent: reg [3:0] answer_reg; always @*

问题 I've gotten in the habit of developing a lot testbenches and use for() and while() loops for testing purpose. Thats fine. The problem is that I've taken this habit over to coding for circuits which should be synthesizable. XST and others refuse to synthesize code (without additional modification to synthesis parameters) such as: while (num < test_number) begin . . . num = num+1; end This is bad coding style because to the synthesizer test_num is an int with value 2^32! or it sees it as

问题 I am trying to use a Verilog preprocessor macro in Altera Quartus requiring use of a parameter value inside a variable name. Example: `define INCREMENT_COUNTER(parsername) \ __parsername_counter <= __parsername_counter + 4'h1; So using `INCREMENT_COUNTER(p1) should give __p1_counter <= __p1_counter + 4'h1; However parsername is not properly replaced and returns __parsername_counter <= __parsername_counter + 4'h1; I have also tried using __``parsername``_counter <= __``parsername``_counter + 4

问题 I have a question about what seems to me odd behavior of an AGC/SPI controller I'm working on. It's done in Verilog, targeting a Xilinx Spartan 3e FPGA. The controller is a FSM that relies on external inputs to start. The state of the FSM is stored in state_reg which is not explicitly initialized, as I thought an uninitialized register would default to zero. When I implemented the controller the FSM would not run. Monitoring the SPI bus I observed no activity. To monitor the FSM i routed the

问题 I am somewhat new to verilog, I tried running this code but it gives me an error: module enc(in,out); input [7:0] in; output [3:0] out; reg i; reg [3:0] out; always @* begin for (i=0;i<7;i=i+1) begin if ((in[i]==1) && (in[7:i+1]==0)) out = i; else out = 0; end end endmodule I think it complains about in[7:i+1] but i don't understand why ? Can someone please advise.. EDIT ok so I am reluctant to using the X due to their numerous problems.. I was thinking of modifying the code to something like

问题 Assuming I have a register reg [15:0] my_reg , which contains a 16-bit signed sample: How can I find the place where the first bit change is located? Meaning, that if assuming that my_reg = 16'b0001011011010111 , how can I know that the first change from 0 to 1 is at my_reg [12] ? Same for numbers starting with 1 ,negative numbers, e.g. my_reg = 16'b1111011011010111 would be interested in the position of the first appearing 0 (which is 11 in this case). The ultimate goal (to add a little bit

问题 I posted an answer to another stackoverflow question which requires some digital logic to be implemented in Verilog or VHDL so that it can be programmed into an FPGA. How would you implement the following logic diagram in Verilog, VHDL, or any other hardware description language? The numbered boxes represent bits in a field. Each field has K bits, and the bits for current and mask will be provided by a computer system (using a latched register or equivalent). The bits in next will be read

问题 I am trying to create a for loop that assigns different values to a logic array given the iteration of the loop. So, for instance, let's say I am trying to instantiate two different bricks, both with a width of 10 and height of 5. Let's also say that each of these values are 10 bits. For two bricks, I have the code: logic[19:0] Brick_Width; logic[19:0] Brick_Height; Where the first brick's width and height will be assigned into the most significant 10 bits and the second's in the least

问题 I'm having trouble figuring out how to translate this VHDL code to Verilog. v_Upper := r_Digit_Index*4 + 3; v_Lower := r_Digit_Index*4; v_BCD_Digit := unsigned(r_BCD(v_Upper downto v_Lower)); if v_BCD_Digit > 4 then v_BCD_Digit := v_BCD_Digit + 3; end if; r_BCD(v_Upper downto v_Lower) <= std_logic_vector(v_BCD_Digit); If I try doing this in Verilog, I get the error, "Range Must be Bound by Constant Expression." I understand the error, but I can't figure out a good way to get around this.