Verilog range must be bounded by constant expression

问题

I'm having trouble figuring out how to translate this VHDL code to Verilog.

v_Upper     := r_Digit_Index*4 + 3;
v_Lower     := r_Digit_Index*4;
v_BCD_Digit := unsigned(r_BCD(v_Upper downto v_Lower));

if v_BCD_Digit > 4 then
  v_BCD_Digit := v_BCD_Digit + 3;
end if;

r_BCD(v_Upper downto v_Lower) <= std_logic_vector(v_BCD_Digit);

If I try doing this in Verilog, I get the error, "Range Must be Bound by Constant Expression." I understand the error, but I can't figure out a good way to get around this. Essentially I want to parse a specific nibble of r_BCD, update it if it needs updating, then write it back into the same location that I pulled it from. Would a 2D array be better here?

Here's the line of Verilog code causing the problem:+

r_BCD[r_Digit_Index*4 + 3:r_Digit_Index*4] <= w_BCD_Digit + 3;

回答1:

In verilog you can not have a variable selection like that.

ie r_BCD[r_Digit_Index*4 + 3:r_Digit_Index*4] is not allowed.

Since 2001 you can do variable part-select using the special +: syntax.

for example :

r_BCD[r_Digit_Index*4 +: 4] 
   //[ index          +: width]  

For more info see Sutherland 2001 part 1-48.

来源：https://stackoverflow.com/questions/25123924/verilog-range-must-be-bounded-by-constant-expression