verilog

问题 I am trying to write a BCD Adder in Verilog, but I am having trouble with one of the modules. Specifically, the adder that takes two BCD digits and adds them. So, the idea is if the sum of the two digits is less than or equal to nine, then it is correct. However, if it is greater, then an offset of 6 has to be added. Here is my Verilog code so far: module DIGITADD( input [3:0] IN_A, input [3:0] IN_B, input CIN, output reg COUT, output reg [3:0] SUM ); wire s2, c2; always @ ( * ) begin assign

问题 I am new with Eclipse, I have used it for SW development and in Altra environment for Nios processor. But now, I have a pretty large project that I have to manage and I would like to use Eclipse to have all the files in the system to make it easier to manage and update. The project has multiple directories for various IPs and has multiple targets for ASCI, Xilinx and Altera FPGAs. In a near future the project will support both NIOS, Microblaze and ARM processors and I would really like to

问题 I have a serial output of a verilog module I'd like to testbench using system-verilog. The output, called 'SO' will output something like 8'hC6 given the correct serial input 'SI' with a value of say 8'h9A. Is there an easy way to encode / decode serial IOs without having to explicitly describe each signal? For example: assert property @(posedge clk) $rose(EN) |-> ##[1:3] SI ##1 !SI[*2] ##1 SI[*2] ##1 !SI ##1 SI ##1 !SI ##[1:3] SO[*2] ##1 !SO[*3] ##1 SO[*2] ##1 !SO; It looks like a jumbled

问题 I need to read a small image (tif format) from PC to FPGA kit (ALTERA DE2-70) for processing, then write it back to PC. I have no idea how to do it in Verilog? Can it be done in C? if so, how can I combine my C/HDL code to work together? Thank you! 回答1: a few mounts ago i were having the same problem, but i wanted to send and receive a real time image. back then i was researching and the best (fast an chip) solution that i find was the XEM6001 of opalkelly. http://www.opalkelly.com/products

问题 i have a verilog code in which there is a line as follows: parameter ADDR_WIDTH = 8 ; parameter RAM_DEPTH = 1 << ADDR_WIDTH; here what will be stored in RAM_DEPTH and what does the << operator do here. 回答1: << is a binary shift, shifting 1 to the left 8 places. 4'b0001 << 1 => 4'b0010 >> is a binary right shift adding 0's to the MSB. >>> is a signed shift which maintains the value of the MSB if the left input is signed. 4'sb1011 >> 1 => 0101 4'sb1011 >>> 1 => 1101 Three ways to indicate left

问题 I am clock gating some latch and logic in my design. I don't have much experience in synthesis and place & route. What is the proper way to implement clock gating in RTL? Example1: always_comb begin gated_clk = clk & latch_update_en; end always_latch begin if(gated_clk) begin latch_data <= new_data; end end Example2: I stumbled into a RTL examples while doing some research about good practices in RTL clock gating. That example implemented the above code like this: clock_gator cg_cell (.clk

问题 Suddenly, I am made to look into some verilog testbench code which heavily uses $readmemh, and $writememh. I understood that it basically read to memory and write to memory. I will be happy if you can point to some resources related to those routines. PS: I searched in google for no success. (I am very ... very new to Verilog) 回答1: I agree its not too easy to find something about readmem/writemem. You can find a little bit here: http://fullchipdesign.com/index_files/readmemh.htm Anyway there

问题 I'm writing a project with Verilog and want to use parameter to define some parameter in my module. But when I read in some source code, localparam sometimes is used instead of parameter . What's difference between them? 回答1: Generally, the idea behind the localparam (added to the Verilog-2001 standard) is to protect value of localparam from accidental or incorrect redefinition by an end-user (unlike a parameter value, this value can't be modified by parameter redefinition or by a defparam

问题 I have tried to design a Booth multiplier and it runs well in all compilers including: Modelsim,Verilogger Extreame,Aldec Active Hdl & Xilinx's Isim. ..... I know Simulation and Synthesis are two Different Process and only few Verilog constructs with various restrictions are there for synthesis. But I don't know what happen While loop in my program not work in Synopsys Synplify 9.6 as well as in Xilinx ise 14.2 . When I try to synthesize Synopsys says "loop iteration limit 2000 exceeded"

问题 This question already has answers here : Using wire or reg with input or output in Verilog (5 answers) Closed 3 years ago . I'm confused about reg and wire when I was doing my homework. I could not understand differences between reg and wire exactly. Can you explain shortly? Also, I wonder that what will happen when I use output q instead of output reg q ? 回答1: In simulation , a Verilog wire behaves like a piece of metal, a track, a wire, whilst a Verilog reg is a variable, it is storage*.