Verilog preprocessor string concatenation

问题

I am trying to use a Verilog preprocessor macro in Altera Quartus requiring use of a parameter value inside a variable name.

Example:

`define INCREMENT_COUNTER(parsername) \
__parsername_counter <= __parsername_counter + 4'h1;

So using `INCREMENT_COUNTER(p1) should give

__p1_counter <= __p1_counter + 4'h1;

However parsername is not properly replaced and returns

__parsername_counter <= __parsername_counter + 4'h1;

I have also tried using

__``parsername``_counter <= __``parsername``_counter + 4'h1;

which doesn't work either. Any help would be appreciated.

回答1:

`` works in VCS and Incisive, but I don't know about Quartus:

module tb;

reg clk = 0;
always #5 clk = ~clk;

reg [3:0] __foo_counter = 0;

`define INC_CNT(name) __``name``_counter <= __``name``_counter + 1;

always @(posedge clk) `INC_CNT(foo)

initial begin
    $monitor($time, " clk=%b cnt=%d", clk, __foo_counter);
    #55 $finish;
end

endmodule

/*

Outputs:

                   0 clk=0 cnt= 0
                   5 clk=1 cnt= 1
                  10 clk=0 cnt= 1
                  15 clk=1 cnt= 2
                  20 clk=0 cnt= 2
                  25 clk=1 cnt= 3
                  30 clk=0 cnt= 3
                  35 clk=1 cnt= 4
                  40 clk=0 cnt= 4
                  45 clk=1 cnt= 5
                  50 clk=0 cnt= 5
*/

回答2:

I know this is a bit old, but the correct answer is that concatenation is available till SystemVerilog.

So if someone wants to use it: Settings->Analysys & Synthesis Settings->Verilog HDL and check the SystemVerilog

Some of simulators may use it regardless of the choosen standard (like Icarus), which might be a little confusing.

回答3:

I was able to use {"a","b"} syntax to concatenate in a macro with params.

For example:

`define DEFAULT_CS_PATH(x,y) {"../../../fpgas/cs/", x, "/build/tmp/scalar", y, ".mif"}

cs20_top #(
               .SCALAR_MEM_0 (`DEFAULT_CS_PATH("cs20","0")),
               .SCALAR_MEM_1 (`DEFAULT_CS_PATH("cs20","1")),
               .SCALAR_MEM_2 (`DEFAULT_CS_PATH("cs20","2")),
               .SCALAR_MEM_3 (`DEFAULT_CS_PATH("cs20","3")))
        cs20_top (
            .CLK                (clk),

            ...
);

来源：https://stackoverflow.com/questions/26288793/verilog-preprocessor-string-concatenation

标签

verilog