error on verilog instance?

问题

I want to compile this Verilog code but i had error in instance of B module in MultiP module. error 1: Undefined variable B. error 2: near "Adder1": syntax error, unexpected IDENTIFIER.

Code:

 module A(x,y,ci,co,sum);
     input x,y,ci;
     output co,sum;  
     reg co,sum;

     always @(x | y | ci)
       begin
       sum = x ^ y ^ ci;
       co = (x & y) | (ci & y ) | (ci & x);
     end  
endmodule

module B(ppk,x,y,ci,co,ppko);
  input x,y,ppk,ci;
  output ppko,co;
  reg ppko,co;

  always @(x | y | ci | ppk)
    begin
      A((x & y),ppk,ci,co,ppko);
   end 
endmodule

module MultiP(x,y,ppko);
  input [3:0] x;
  input [3:0] y;
  output [7:0] ppko;
  wire [12:0] cW;
  wire [12:0] ppW;

  always @(x | y )
  begin

    B Adder1( (x[0]&y[1]) , y[0], x[1], 0     , cW[0] , ppko[1] );
    B Adder2( (x[0]&y[2]) , y[1], x[1], cW[0] , cW[1] , ppW[0]  );
    B Adder3( (x[0]&y[3]) , y[2], x[1], cW[1] , cW[2] , ppW[1]  );
    B Adder4( 0           , y[3], x[1], cW[2] , cW[3] , ppW[2]  );

    B Adder5( ppW[1] , y[0] , x[2] , 0     , cW[4] , ppko[2] );
    B Adder6( ppW[2] , y[1] , x[2] , cW[4] , cW[5] , ppW[3]  );
    B Adder7( ppW[3] , y[2] , x[2] , cW[5] , cW[6] , ppW[4]  );
    B Adder8( cW[3]  , y[3] , x[2] , cW[6] , cW[7] , ppW[5]  );

    B Adder9( ppW[3] , y[0] , x[3] , 0      , cW[8]   , ppko[3] );
    B Adder10( ppW[4] , y[1] , x[3] , cW[8]  , cW[9]   , ppko[4] );
    B Adder11( ppW[5] , y[2] , x[3] , cW[9]  , cW[10]  , ppko[5] );
    B Adder12( cW[7]  , y[3] , x[3] , cW[10] , ppko[7] , ppko[6] );

  end

endmodule

回答1:

I made minimal changes to your code to get it to compile:

module A(x,y,ci,co,sum);
     input x,y,ci;
     output co,sum;
     reg co,sum;

     always @* begin
       sum = x ^ y ^ ci;
       co = (x & y) | (ci & y ) | (ci & x);
     end
endmodule

module B(ppk,x,y,ci,co,ppko);
  input x,y,ppk,ci;
  output ppko,co;
  reg ppko,co;

    A A ((x & y),ppk,ci,co,ppko);
endmodule

module MultiP(x,y,ppko);
  input [3:0] x;
  input [3:0] y;
  output [7:0] ppko;
  wire [12:0] cW;
  wire [12:0] ppW;

    B Adder1( (x[0]&y[1]) , y[0], x[1], 0     , cW[0] , ppko[1] );
    B Adder2( (x[0]&y[2]) , y[1], x[1], cW[0] , cW[1] , ppW[0]  );
    B Adder3( (x[0]&y[3]) , y[2], x[1], cW[1] , cW[2] , ppW[1]  );
    B Adder4( 0           , y[3], x[1], cW[2] , cW[3] , ppW[2]  );

    B Adder5( ppW[1] , y[0] , x[2] , 0     , cW[4] , ppko[2] );
    B Adder6( ppW[2] , y[1] , x[2] , cW[4] , cW[5] , ppW[3]  );
    B Adder7( ppW[3] , y[2] , x[2] , cW[5] , cW[6] , ppW[4]  );
    B Adder8( cW[3]  , y[3] , x[2] , cW[6] , cW[7] , ppW[5]  );

    B Adder9( ppW[3] , y[0] , x[3] , 0      , cW[8]   , ppko[3] );
    B Adder10( ppW[4] , y[1] , x[3] , cW[8]  , cW[9]   , ppko[4] );
    B Adder11( ppW[5] , y[2] , x[3] , cW[9]  , cW[10]  , ppko[5] );
    B Adder12( cW[7]  , y[3] , x[3] , cW[10] , ppko[7] , ppko[6] );
endmodule

As Marty mentioned, I replaced the always block sensitivity list In module A with *. I got rid of the always blocks around your A and B instances. I added an instance name for the A instance.

回答2:

I would say there are other more subtle problems with the code.

First of all it is a good practice to make sure that no implicit nets are declared. Otherwise misspelled net names can cause singe bit nets to be automatically created with strange behavior as a result

`default_nettype none

Then I advice to have the net type declarations of the port nets in the port declaration of the module

module A(input wire x,
     input wire y,
     input wire ci,

     output reg co,
     output reg sum);

   always_comb begin //Use this if you have a system verilog compiler
   always @* begin //Use @* as suggested otherwise 
      sum = x ^ y ^ ci;
      co = (x & y) | (ci & y ) | (ci & x);
   end  
endmodule

module B(input wire ppk,
     input wire x,
     input wire y,
     input wire ci,

     output reg co,
     output reg ppko);

Also I would strongly recommend that you use the named parameter instantiation as follows.

   A a(.x(x&y),
       .y(ppk),
       .ci(ci),
       .co(co),
       .ppko(ppko));

endmodule

module MultiP(input wire  [3:0] x,
          input wire  [3:0] y,
          output reg [7:0] ppko);

  wire [12:0] cW;
  wire [12:0] ppW;

   B Adder1(.ppk(x[0]&y[1]),
        .x(y[0]), 
        .y(x[1]), 
        .ci(0), 
        .co(cW[0]), 
        .ppko(ppko[1]));

... //The rest of all B instantiations

endmodule

And as said earlier module instantiations are not done in always blocks.

I think you need to read a good book about Verilog. Personally I learned from Verilog HDL http://www.amazon.com/Verilog-HDL-paperback-2nd-Edition/dp/0132599708/ref=sr_1_1?ie=UTF8&qid=1362691992&sr=8-1&keywords=verilog+hdl

来源：https://stackoverflow.com/questions/15281082/error-on-verilog-instance

标签

verilog