Difference between wire and reg

问题

I'm new in Verilog and i have question that i don't understand:

module my_func(t0, t1, t2, t3, s0, s1, res)
begin
  in t0, t1, t2, t3, s0, s1;
  out res;

  always begin
    if ( s0=0 && s1=0 )   res = t0;
    if ( s0=1 && s1=0 )   res = t1;
    if ( s0=0 && s1=1 )  res = t2;
    if ( s0=1 && s1=1 )   res = t3;
  end
endmodule

module my_FSM( input, output )
begin
  in input;
  out output;
  ¬¬__(1)__ d[3];
  __(2)__ q[3];

always @ (in)
begin
  d[0] = input | q[2];
  d[1] = input & q[0];
  my_func(0, q[0], q[1], q[2], q[1], input, d[2]);
  out = q[2] & d[1];
end

always @(posedge clk)
begin
  q = d;
end

endmodule

The question is:

FILL The missing:
(1): wire, (2): reg (this is the truth answer )

Can someone explain why this the true answer and what the different between wire and reg?

回答1:

wire declarations technically aren't required in Verilog, unless you have overridden `default nettype, but I imagine that's not what is desired. But remember that things assigned in an always block must be of type 'reg'.

Good luck.

来源：https://stackoverflow.com/questions/29965504/difference-between-wire-and-reg