Comparing input signal with array values

问题

As I wrote in my previous post Synthesizable array of XY values I wanted to create an array in Verilog to store x, y values of a given function.

Now I want to compare an input with x values of this array. If the value is within a specific region I want to save the index of this region and perform an addition with y with the same index. The result goes to the output. The code compiles just fine but its not synthesizes any circuit. The idea later is to use this array to perform linear interpolation and determinate the value of y for a given value of x that its not inside the array. The code is the following. I save the save value for x and y for each index.

 module memc (inp,outp,clk,reset);
    input[2:0] inp;
    input clk, reset; 
    output[2:0] outp;
    reg[2:0] outp;
    wire [2:0] test;
    reg [5:0] mem[2:0];

always @(posedge clk)
if (reset == 1'b1) begin
    mem[0] <= {3'b000, 3'b000};//y0,x0
    mem[1] <= {3'b001, 3'b001};//y1,x1
    mem[2] <= {3'b010, 3'b010};//y2,x2
end


assign test ={inp<mem[0][2:0],inp<mem[1][2:0],inp<mem[2][2:0]}; //create a test vector by comparing inp with xo,x1,x2
always @(test)
case (test)
3'b1xx: outp=mem[0][2:0]+mem[0][5:3];//if 0<inp<x1
3'b0xx: outp=mem[1][2:0]+mem[1][5:3];//if x1<inp<x2
3'b00x: outp=mem[2][2:0]+mem[2][5:3];//if x2<inp<x3
default: outp=3'b00;
endcase
endmodule

回答1:

Firstly, all three of your if conditions are the same (inp > mem[0][2:0]). I'm assuming you want

always @(*) 
begin 
    if (inp > mem[0][2:0] )  //index 0
    begin
        index = 0;
    end 
    else if (inp > mem[1][2:0] )  // index 1
    begin
        index = 1;
    end 
    else if(inp > mem[2][2:0] ) // index 2
    begin 
        index = 2;
    end 
end

Secondly, if you are using a large array (hard to be exact on the size), the latency from inp -> outp will get quite long, and you may get timing violations, depending on your clock speed. In that case, you'd be better off building a very simple FSM, and checking one or two entries per clock cycle instead. Just something to keep in mind moving forward.

来源：https://stackoverflow.com/questions/30037741/comparing-input-signal-with-array-values

标签

arrays

verilog