better alternative on for loop verilog

问题

I am a newbie in verilog. I have been searching online and most of them suggest to not use for-loop in verilog coding. So is there a better alternative to replace for-loop? The problem that I am facing now is that I need to perform 1 or 2 for-loop in a case statement. And I have been thinking of better alternatives but come up with none. It will be great if any one of you can shed some light on this.

Example of my code:

always @(*)
case (help)
4'd1: for (i=A; i<=20;i=i+B)
       begin temp[i-1]=1; end
4'd2: for (i=A; i<=20;i=i+B)
        begin temp[i-1]=1; B=B+1; end
4'd3: begin
       for (i=A; i<=20;i=i+B)
        begin temp[i-1]=1; B=B+1; end
       for (i=A; i>=1;i=i-B)
        begin temp[i-1]=1; B=B+1; end
      end
default: temp = 0;

回答1:

For-loops are fine in Verilog, but they need to able to static unroll if you plan on synthesizing. Static unroll means the the the loop is not depended on any external variables. For example for(i=0;i<10;i=i+1) is static. for(i=A; i<=20;i=i+B) is not static as it is a depends on the variables A and B.

You can make a loop static my moving the variables as a condition inside the for-loop. for(i=A; i<=20;i=i+B) becomes:

tmp_var = A;
for (i=0; i<=20;i=i+1) begin
  if (i==tmp_var) begin
    // ... your logic here ...
    tmp_var = tmp_var+B;
  end
end

Issues that need to be addressed beyond the scope of the question:

They way you are using B and temp is a little concerning.

B appears to be an input, but you are also incrementing it. For synthesis it is illegal to manipulate an input. If it is an input, then create a local variable with default value as B and you may change this value later in the within same always block. If it is not an input, then it is creating latching logic; which is not good and I will cover that next with temp.
temp is latching logic. Latching logic are troublesome because timing is critical; knowing when the latch is transparent or closed, and respecting the hold time requirements. The more complex the logic the harder it is to predict. In RTL one way latches are inferred is by incomplete assignments inside an combinational blocks (ie always @*). To resolve this, make sure every bit is assigned each pass of the combinational blocks. One way to safe guard this is to assign default values before staring your logic. Example:
```
always @(*) begin
  temp = 0; // default to a constant
  temp_B = B; // default to an input value

  // ... your logic ...
end
```

来源：https://stackoverflow.com/questions/29082193/better-alternative-on-for-loop-verilog

标签

for-loop

verilog