Using inouts with wand | 易学教程

问题

Consider the below code.

module TriState
  (
   // Outputs
   O, 
   // Inouts
   IO, 
   // Inputs
   OE, I
   );

   parameter          width = 1;


   input              OE;

   input [width-1:0]  I;
   output [width-1:0] O;

   inout [width-1:0]  IO;

   assign             IO = (OE) ? I : { width { 1'b1 } };
   assign             O  = IO;

endmodule // TriState

module m1(.a(inout line_P1$IO));
reg val_P1 ;
wire line_P1$IO,line_P1$O;
TriState #(.width(32'd1)) line_SCL(.I(val_P1),
                 .OE(1),
                 .O(line_P1$O),
                 .IO(line_P1$IO));
always @(*) begin
val_P1 <= 1;
end
endmodule //m1

module m2(.a(inout line_P1$IO));
reg val_P1 ;
wire line_P1$IO,line_P1$O;
TriState #(.width(32'd1)) line_SCL(.I(val_P1),
                 .OE(1),
                 .O(line_P1$O),
                 .IO(line_P1$IO));
always @(*) begin
val_P1 <= 0;
end
endmodule //m2

module top();

wand P1;
assign P1 = 1;

m1 ins1(.a(P1));
m2 ins2(.a(P1));
endmodule //top

I am sorry, i know this is lot of code but to build a test scenario I wasn't able to think of smaller than this. Now the problem is when the above code is simulated,

The value of variables are the following In m1,

tristate , I = 1, as expected.

. , IO = 0, unexpected as IO = I ?

. , O = 0 ;//= IO as expected

. , OE = 1 // obviously

In m2,

tristate , I = 0, as expected.

. , IO = 0, expected as IO = I

. , O = 0 ;//= IO as expected

. , OE = 1 // obviously

Now I don't understand how the value of IO in m1 is 0 ? Is it because I am passing wand as argument to inout, does that make inout a wand type, if that so it begs the following question ,

A link to my another question on stackoverflow

I asked the (question in link) first but there were some clarification which needed to be added,so I added the clarification portion in terms of a new question. Basically I want to know how is it that inout is behaving like wand, and if so, how do I make inout behave like wand without using a different top module to instantiate .

回答1:

This syntax is incorrect:

module m1(.a(inout line_P1$IO));

you should do

module m1(.a(line_P1$IO));
    inout line_P1$IO;

in ansi standard it should be

module m1(inout .a(line_P1$IO));

though I tried ansi version in 'vcs' and was not implemented there. Non-ansi worked.

来源：https://stackoverflow.com/questions/45181310/using-inouts-with-wand

标签

verilog

inout