verilog

问题 I'm very new to Verilog HDL and I have to code this 4bit up down counter. With the help of some reading on up-down counters and t flipflops, I already made the following code: module up_down_4bitcounter ( out, up_down, clk, data, reset ); //Output Ports output [3:0] out; //Input Ports input [3:0] data; input up_down, clk, reset; //Internal Variables reg [3:0] out; //Start of Code always @(negedge clk) if (reset) begin // active high reset out <= 4'b0 ; end else if (up_down) begin out <= out +

问题 I have some tasks in verilog file. And I want to see them in simvision when they are triggered. Is there any way to find task's triggered point in simvision? Is this can not be able to visualize in simvision? I know that manner like using print or display statements. But I need to visualize to simvision. Does anyone know that way? UPDATE Use a breakpoint If you don't have access to the source of the task, or cannot modify it, >you could set a breakpoint when the task is called, execute some

问题 I'm new to verilog and I am doing a project for my class. So here is my code: wire [n-1:0] subcounter_of_counter; reg [n-1:0] mask,free; //subcounter_of_counter: dinei ena vector apo poious subcounter apoteleitai o counter(id) always @(*) begin //command or id or mask or free or subcounter_of_counter if (command==increment) begin for (int i = 0; i < n; i=i+1)begin if (i<id) begin subcounter_of_counter[i]=1'b0; end else if (i==id) begin subcounter_of_counter[i]=1'b1; end else begin if( (|mask

问题 I'm trying to write a top-level module in Verilog that will open a water valve whenever a sensor reads values below a certain number. Here is my code: module ProjectDSD(alteraClock, sensorInput, openValve); input sensorInput, alteraClock; output openValve; always @(sensorInput) begin if(sensorInput < 100) //sensor value to irrigate at begin openValve <= 1; //here end else begin openValve <= 0; //here end end endmodule Im getting an error saying: Object "openValve" on left-hand side of

问题 I'm new to Verilog and would really appreciate it if someone could help me with this. I have a task written in a separate file - "task.v" : module task_create(); task assign_inp; reg a,b,c,d; //details endtask endmodule I have a module that is calling this task: module tb(); `include "task.v" assign_inp(a,b,c,d); endmodule When I execute this, I get this error: Module definition task_create cannot nest into module tb When I remove the module and endmodule in task.v, I get this error: Task

问题 I am working on designing a finite state machine in Verilog to represent a stack. The module is as follows: module state_machine (s, Enable, Clock, Resetn, c, OF_Err, UF_Err); input [2:0] s; input Enable, Clock, Resetn; output reg [1:0] c; output reg OF_Err = 0, UF_Err = 0; reg [2:0] y, Y; parameter [2:0] A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E = 3'b100; always @(s, y, Enable) if (Enable) begin case (y) A: if (s == 3'b000) Y = B; else begin Y = A; UF_Err = 1; end B: if (s == 3'b000)

问题 I've looked over my code, and I see nothing wrong. Here's the specific error, any help appreciated: ERROR:HDLCompilers:26 - "myGates.v" line 33 expecting 'endmodule', found 'input' Analysis of file <"myGates.prj"> failed. module myGates( input sw0, input sw1, input sw2, input sw3, output ld0, output ld1, output ld2, output ld3, output ld7 ); input sw0, sw1, sw2, sw3; output ld0, ld1, ld2, ld3, ld7; wire w1, w2; assign ld0 = sw0; assign ld1 = sw1; assign ld2 = sw2; assign ld3 = sw3; and u1 (w1

问题 I have written a Verilog code, this code to describe a combinational module. I used a blocking assignment. in other parts, there is must use a nonblocking assignment. can I use a delay in the blocking assignment to be alternative to a nonblocking assignment... I don't want to mix these two assignments in one module `timescale 1ns / 1ps module buffer(datain1,datain2,datain3,datain4, s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12, src_out1,src_out2,src_out3, src_out4,src_out5,src_out6, src_out7,src

问题 I have never come across this problem before when uses black-boxes inside custom IP. Usually I instantiate and add the custom IP to the project, and then instantiate and add the black box IP modules (the black boxes are inside the custom IP) to the project. For some reason now I am getting the classic [Project 1-486] Could not resolve non-primitive black box cell 'FX_Thomas_Core_0FX_Thomas_Core_0FX_Thomas_Core_0Thomas_Sub' instantiated as 'Subtractor' ["c:/Users/Sam/Documents/Zynq7020/FX

问题 I am trying to successively subtract a particular number to get the last digit of the number (without division). For example when q=54, we get q=4 after the loop. Same goes for q=205, output is q=5. if(q>10) while(q>10) begin q=q-10; end The iteration should converge logically. However, I am getting an error: "[Synth 8-3380] loop condition does not converge after 2000 iterations" I checked the post - Use of For loop in always block. It says that the number of iterations in a loop must be