Verilog 4-bit up-down counter designed using negative edge triggered T flip flops

问题

I'm very new to Verilog HDL and I have to code this 4bit up down counter. With the help of some reading on up-down counters and t flipflops, I already made the following code:

module up_down_4bitcounter (
out,
up_down,
clk,
data,
reset
);

//Output Ports
output [3:0] out;

//Input Ports
input [3:0] data;
input up_down, clk, reset;

//Internal Variables
reg [3:0] out;

//Start of Code
always @(negedge clk)
if (reset) begin // active high reset
out <= 4'b0 ;
end else if (up_down) begin
out <= out + 1;
end else begin
out <= out - 1;
end

endmodule 

Now, I'm getting this error:

Exercise5_1.v:25: syntax error
Exercise5_1.v:25: error: unmatched character (')
Exercise5_1.v:25: error: malformed statement

Line 25 is this one:

out <= 4'b0 ;

I am not 100% sure if my coding is correct. Can you tell me where my issue is?

回答1:

Line 25 is this one:

There is an error at line 25:

out <= 4'b0 ;

Answer is:

Out <= 4'b0000 ;

回答2:

Your code is fine, you can simulate it here. One option is changing the out <= 4'b0; to out <= 0;, and if it works there is something wrong with either your editor or simulator.

来源：https://stackoverflow.com/questions/30667787/verilog-4-bit-up-down-counter-designed-using-negative-edge-triggered-t-flip-flop